This paper presents an updated perspective on the design and implementation of radio access protocols in wireless ATM networks. The protocol architecture of a wireless ATM network is outlined with particular focus on the radio access subsystem consisting of radio physical level (PHY), medium access control (MAC), data link control (DLC) and wireless control. Each of these protocol layers in wireless ATM is described and preliminary performance/experimental results are given where applicable. Hardware and software implementation details are given for the "WATMnet2.0" 25 Mbps/5 GHz WATM radio network interface card currently under development, and associated mobile terminal and base station architectures are discussed.

A prototype microcellular wireless asynchronous transfer mode network (WATMnet) capable of providing integrated multimedia communication services to mobile terminals is described in this paper. The experimental system's hardware consists of laptop computers (NEC Versa-M) with WATMnet interface cards, multiple VME/i960 processor-based WATMnet base stations, and a mobility-enhanced local-area ATM switch. The prototype wireless network interface cards operate at peak bit-rates up to 8 Mb/s, using low-power 2.4 GHz industrial, scientific, and medical (ISM)-band modems. Wireless network protocols at the portable terminal and base station interfaces support available bit rate (ABR), variable bit rate (VBR), and constant bit rate (CBR) transport services compatible with ATM using a dynamic time-division multiple-access/time-division duplex (TDMA/TDD) MAC protocol for channel sharing and data link control (DLC) protocol for error recovery. A custom wireless control protocol is also implemented between the portable and base units for support of radio link related functions such as user registration and handoff. All network entities including the portable, base and switch use a mobility-enhanced version of ATM ("Q.2931+") signaling for switched virtual circuit (SVC) connection control functions, including handoff. In the first stage of the prototype, the application-level API is TCP/UP over ATM ABR service class using AAL5. Early experiments with the WATMnet prototype have been conducted to validate major protocol and software aspects, including DLC, wireless control, and mobility signaling for handoff, Selected network-based multimedia/video applications requiring moderate bit-rates (/spl sim/0.5-1 Mb/s) in the ABR mode have been successfully demonstrated on the laptop PC.

Wireless ATM networks will provide multimedia information to end users anywhere and anytime. A key technology component in the integration of a wireless ATM (WATM) network is the WATM network interface card (NIC). Similar to ATM NICs, the WATM NIC requires the support of the ATM and AAL layer transfer protocols. But, in order to provide a reliable wireless transmission platform, WATM NICs should also incorporate data link control (DLC), media access control (MAC), and radio physical (RPhy) layer functionality. As a result, the WATM NICs processing requirements are more demanding than that of ATM NICs at equivalent transmission rates. Thus, the design of a high-performance WATM NIC software/hardware low-cost architecture poses a new challenge. This paper presents a new architecture and implementation of a first generation 8 Mb/s WATM NIC developed at NEC Princeton for the WATMnet network.

The analysis and development of ATM network traffic control algorithms is often performed using theoretical traffic models. Algorithms for traffic shaping, policing, flow control, and switch architectures have been proposed based on these models. While the models help to obtain preliminary solutions, the success and validity of the proposed algorithm will be a function of how close the assumed models resemble real traffic patterns. The paper presents ATMTraP, an experimental prototype asynchronous transfer mode traffic and performance measurement tool which could be used in the characterization of sources and elements that form the ATM network. ATMTraP has been used in the Nectar Gigabit Testbed to collect preliminary traffic statistics from sources, such as, a Cray C-90 supercomputer, Sun workstations, and an iWARP systolic array.

The authors describe the architecture of an experimental research prototype application specific integrated circuit (ASIC) designed to serve as a generic building block of the future broadband integrated services digital network (B-ISDN). The chip performs common asynchronous transfer mode (ATM) layer functions such as cell assembly and cell disassembly. A new media access control (MAC) protocol developed for a broadband customer premises network is also integrated in the chip. The chip interfaces to the B-ISDN through a synchronous optical network (SONET) synchronous transmission signal-3c (STS-3c) framer chip. The ATM layer chip has been designed using 1.2 mu m CMOS technology with a die area of 5.4*5.4 mm/sup 2/ and approximately 27000 transistors. Experimental results are described. At the user network interface, the chip can be used to implement broadband terminal adaptors and the network termination. At the broadband local exchange, the chip can be used in the implementation of ATM statistical multiplexers, ATM switch port controllers, etc.>