Demo Data from EDBT 2026 / reviewers in the wild / expert
Charalambos Basetas
dblp:71/5026
· DBLP profile ↗
2ranked-venue papers
0as first author
0since 2021 · last 2013
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Integrated circuit design · 50% Processor architecture and microarchitecture · 22% Energy-efficient computing · 22% |
Topics — the 6 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Processor architecture and microarchitecture
computer arithmetic |
0.2 | 1 | 2013 | Low-Power Logarithmic Number System Addition/Subtraction and Their Impact on Digital Filters · IEEE Trans. Computers 2013 |
Integrated circuit design › digital circuit design › arithmetic circuit design
logarithmic number system |
0.2 | 1 | 2013 | Low-Power Logarithmic Number System Addition/Subtraction and Their Impact on Digital Filters · IEEE Trans. Computers 2013 |
Energy-efficient computing › low-power design
low-power arithmetic circuit |
0.2 | 1 | 2013 | Low-Power Logarithmic Number System Addition/Subtraction and Their Impact on Digital Filters · IEEE Trans. Computers 2013 |
Integrated circuit design
low-power circuit design |
0.2 | 1 | 2013 | Low-Power Logarithmic Number System Addition/Subtraction and Their Impact on Digital Filters · IEEE Trans. Computers 2013 |
Integrated circuit design › digital signal processing circuits
digital filter |
0.0 | 1 | 2013 | Low-Power Logarithmic Number System Addition/Subtraction and Their Impact on Digital Filters · IEEE Trans. Computers 2013 |
Cloud and datacenter computing › resource provisioning
dynamic resource provisioning |
0.0 | 1 | 2013 | Low-Power Logarithmic Number System Addition/Subtraction and Their Impact on Digital Filters · IEEE Trans. Computers 2013 |
Methods — techniques the papers use, named apart from their topics
roundoff noise model · 0.2cotransformation · 0.2
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2013 | Low-Power Logarithmic Number System Addition/Subtraction and Their Impact on Digital FiltersabstractThis paper presents techniques for low-power addition/subtraction in the logarithmic number system (LNS) and quantifies their impact on digital filter VLSI implementation. The impact of partitioning the look-up tables required for LNS addition/subtraction on complexity, performance, and power dissipation of the corresponding circuits is quantified. Two design parameters are exploited to minimize complexity, namely the LNS base and the organization of the LNS word. A roundoff noise model is used to demonstrate the impact of base and word length on the signal-to-noise ratio of the output of finite impulse response (FIR) filters. In addition, techniques for the low-power implementation of an LNS multiply accumulate (MAC) units are investigated. Furthermore, it is shown that the proposed techniques can be extended to cotransformation-based circuits that employ interpolators. The results are demonstrated by evaluating the power dissipation, complexity and performance of several FIR filter configurations comprising one, two or four MAC units. Simulations of placed and routed VLSI LNS-based digital filters using a 90-nm 1.0 V CMOS standard-cell library reveal that significant power dissipation savings are possible by using optimized LNS circuits at no performance penalty, when compared to linear fixed-point two's-complement equivalents. Ioannis Kouretas, Charalambos Basetas, Vassilis Paliouras |
IEEE Trans. Computers | 2 |
| 2008 | Low-power logarithmic number system addition/subtraction and their impact on digital filtersabstractThis paper discusses techniques for low-power addition/subtraction in the logarithmic number system (LNS) and evaluates their impact on digital filter implementation. Initially, the impact of partitioning the look-up tables (LUT) required for addition/subtraction on complexity, performance, and power dissipation is studied. Subsequently techniques for the low-power implementation of an LNS multiply- accumulate (MAC) unit are investigated. The obtained LNS MACs are used for the design of digital filters. Synthesis of LNS-based digital filters using a 0.18 mum 1.8 V CMOS standard-cell library, reveal that significant power dissipation savings are possible at no performance penalty, when compared to linear two's-complement equivalent. Ioannis Kouretas, Charalambos Basetas, Vassilis Paliouras |
ISCAS | 2 |