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Minoru Saeki

dblp:71/5027 · DBLP profile ↗
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4ranked-venue papers
1as first author
0since 2021 · last 2013
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Security and privacy · 4 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Network and information security
4 papers
Hardware security and side channels · 100%
Computer architecture, parallel and distributed computing, and storage systems
4 papers
Integrated circuit design · 100%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design
digital circuit design		 0.242013
A Design Methodology for a DPA-Resistant Cryptographic LSI with RSL Techniques · CHES 2009
On Measurable Side-Channel Leaks Inside ASIC Design Primitives · CHES 2013
Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style · CHES 2006
Hardware security and side channels
side-channel attack		 0.212013
On Measurable Side-Channel Leaks Inside ASIC Design Primitives · CHES 2013
Hardware security and side channels
side-channel countermeasures		 0.222009
A Design Methodology for a DPA-Resistant Cryptographic LSI with RSL Techniques · CHES 2009
Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style · CHES 2006
Hardware security and side channels › side-channel leakage
side-channel leakage modeling		 0.112005
DPA Leakage Models for CMOS Logic Circuits · CHES 2005
Integrated circuit design › asynchronous circuit design
dual-rail logic		 0.012006
Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style · CHES 2006
Integrated circuit design › digital circuit design
CMOS circuit design		 0.012005
DPA Leakage Models for CMOS Logic Circuits · CHES 2005

Methods — techniques the papers use, named apart from their topics

side-channel measurement · 0.3RSL (random switching logic) · 0.2DPA evaluation · 0.1DPA leakage modeling · 0.1
YearPublicationVenuePosition
2013 On Measurable Side-Channel Leaks Inside ASIC Design Primitives
Takeshi Sugawara 0001, Daisuke Suzuki, Minoru Saeki, Mitsuru Shiozaki, Takeshi Fujino
 CHES3
2009 A Design Methodology for a DPA-Resistant Cryptographic LSI with RSL Techniques
Minoru Saeki, Daisuke Suzuki, Koichi Shimizu, Akashi Satoh
 CHES1
2006 Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style
Daisuke Suzuki, Minoru Saeki
 CHES2
2005 DPA Leakage Models for CMOS Logic Circuits
Daisuke Suzuki, Minoru Saeki, Tetsuya Ichikawa
 CHES2