A 23–29 GHz power amplifier (PA) based on a stacked field-effect transistor (FET) topology is proposed. To achieve higher output power and gain, the output stage employs a triple-stacked FET design. To improve stacking efficiency, neutralization capacitors are added between the differential common-source (CS) amplifiers to compensate for phase mismatches at the stack nodes. Round-table and vertical gate repetition techniques are applied to achieve a compact layout and enhance the PA’s power density. The proposed PA is fabricated using the 22nm FD-SOI process. Measurement results show that the proposed PA delivers a peak saturated power (Psat) of 19.6 dBm, with a core area of only 0.047 mm2, achieving a power density of 1936.2 mW/mm2.

In recent years, fully-connected hybrid beamforming (FC-HBF) architecture has aroused widespread interest for millimeter wave (mmWave) massive multi-input multi-output (MIMO) communication systems. However, the FC-HBF structure suffers from significant linearity deterioration, limiting its applications in actual mmWave transmitters. To resolve this issue, an effective digital predistortion (DPD) method utilizing analytical multi-input behavioral models is proposed in this paper for linearizing the FC-HBF system. Based on the nonlinearity analysis and behavioral modeling of the array response, three analytical multi-input models are derived by embedding the priori beamforming information in the predistorter. The complexity of the proposed analytical models is significantly reduced compared to the state-of-the-art. Numerical simulations and experimental measurement are carried out on a$4\times 64$mmWave FC-HBF array and$2\times 16$quasi-test platform respectively to validate the performance of the proposed DPDs against the state-of-the-art DPDs, which show significant linearization abilities to compensate for the nonlinear distortions of beam signals. The proof-of-the-concept validations in this paper indicate that the proposed scheme is fully capable of linearizing an mmWave FC-HBF array.

This article presents an ultra-broadband distributed efficient power amplifier (DEPA) with reactance compensation and adaptive biasing. It is illustrated that the bandwidth of the DEPA can be improved apparently by applying a shunt short-circuited stub at the combining point. The principle of such method is that the back-off impedance variation with frequency can be compensated by the reactance of the shunt stub. Besides, to get over the high gain compression of the conventional DEPA, an adaptive biasing scheme is proposed for the auxiliary PAs. A DEPA is implemented in a 0.25-$\mu \text{m}$GaN-HEMT process for validation. The shunt stub is realized by a LC tank equivalently for a compact size. The fabricated DEPA achieves a saturated output power of 41.5–43 dBm and an 8-dB back-off drain efficiency (DE) of 38%–46.8% from 1.8 to 5.4 GHz with a chip size of$3.2\times3.2$mm2. The fractional bandwidth (FBW) is up to 100%. Applying a 100-MHz LTE signal with an 8.5-dB peak-to-average power ratio (PAPR), an average DE of 35%–43% is measured over the entire bandwidth, and adjacent channel power ratio (ACPR) is better than −47 dBc after applying digital predistortion. To the best of our knowledge, the proposed DEPA demonstrates the largest FBW among all reported integrated back-off efficient PAs without using digital techniques or reconfiguration.

This article presents a 24–40-GHz broadband beamforming transmit–receive (T/R) front-end (FE) chip for the next-generation millimeter-wave (mm-wave) communication systems. To achieve multiband coverage in a single beamforming front-end IC, the proposed beamforming chip adopts a unified gain and phase control scheme as well as an asymmetric T/R switch circuit, which simplifies the system design and enables broadband operation in both directions. The vector-modulation-based unified phase and gain control (UPGC) scheme eliminates the standalone variable gain amplifier (VGA) in the front end. The bidirectional impedance transformation T/R switch reduces the insertion loss in the TX path and enables Class-F$^{-1}$operation to improve the bandwidth and efficiency. Based on the proposed UPGC scheme and T/R switch circuit, a high-performance mm-wave front-end chip is implemented using a 0.13-$\mu$m SiGe BiCMOS technology. The fabricated front-end chip achieves 12.9–16.9-dBm maximum output power in TX mode, up to 14.3-dB gain and 7.4–9.2-dB noise figure (NF) in RX mode over the frequency range of 24–40 GHz. In both TX and RX modes, the proposed chip achieved less than 0.4-dB rms gain error and 2.0$^{\circ}$rms phase error. A four-element dual-band phased array module is designed and tested to evaluate the performance of the proposed chip in the 28-and 38-GHz dual-band phased array.

In this paper, a low complexity moving average nested generalized memory polynomial model (MAN-GMP) is proposed for digital predistortion (DPD) of broadband power amplifiers (PAs). As the signal bandwidth increases drastically, the strong nonlinear distortions, especially those induced by the memory effect, are generated from the highly efficient PAs. To compensate for the strong memory effect, a moving average nested envelope memory polynomial (MAN-EMP) model is derived from an accuracy-enhanced GMP model, which offers reduced complexity while suffering from degraded modeling accuracy. The MAN-GMP model is further proposed to improve the modeling accuracy by connecting several memory branches of the MAN-EMP model in parallel. An iterative algorithm is designed to extract the model coefficients efficiently through only one or two iterations. Experimental measurements are carried out on two sub-7 GHz broadband GaN Doherty PAs with up to 200 MHz bandwidth OFDM signals to benchmark the proposed MAN-GMP model against the GMP, the parallel-LUT-MP-EMP (PLUME), the augmented complexity-reduced GMP (ACR-GMP), the generalized twin-nonlinear two-box (GTNTB), and the enhanced Wiener models. The experimental results show that the MAN-GMP model can effectively compensate for the nonlinear distortion of broadband PAs with significant complexity reduction.

In this paper, a novel multi-stream spatial digital predistortion (DPD) technique is proposed to model and linearize the fully-connected (FC) hybrid beamforming (HBF) transmitters. The proposed scheme solves the DPD implementation issue in the FC HBF array by estimating and linearizing the beam signals instead of the individual PAs. In FC HBF systems, significant intermodulation (IMD) between different transmit signals will be generated due to the analog beamforming and combining network upstream of the power amplifiers (PAs). The IMD beams will end up being radiated in different directions and some of them might fall in the linear beam directions. Therefore, multi-input DPD blocks using a practical multi-variable model are constructed for each RF chain to eliminate the complicated inner- and cross-channel IMDs of the beam signals. Simulations on a 4-stream 64-element FC HBF array and experimental tests on a 2-stream 4-element system are carried out to benchmark the proposed DPD technique against the conventional techniques. Better than 13 dB adjacent channel power ratio (ACPR) improvement and 12 dB normalized mean square error (NMSE) improvement have been achieved by the proposed DPD technique.

The coherence theory of electromagnetic waves is introduced into describing the correlation transfer characteristics of a multiple element antenna (MEA). The correlations between its input and output signals rather than the antenna elements are studied. In the case of transmission, the coherence properties of the radiation fields can be expressed by the correlation matrix of the input vectors and the tensor products of the element patterns. On the other hand, when two polarized components of the incident fields are not incoherent, the more general formula should be adopted in reception. The common used version is just a special case. To demonstrate these results, two dipole configurations are simulated.

This letter presents a new array pattern synthesis algorithm using the two-step least-squares method. The algorithm utilizes the randomness of the desired pattern phase to design an array pattern. Several numerical examples are presented to illustrate this algorithm.