The two main issues in the area of the Internet of Things are low resource consumption and secure data transmission. Conjugating both is fairly hard on ensuring security, leading to great efforts in research. The standard cryptography methods currently proposed are based on simplifications of standard protocols, but are still demanding on resources. Chaotic encryption is a way to reduce this burden, while keeping an equivalent level of security. In this paper, we propose, for the first time, a purely digital scheme for chaotic secure communications, able to be implemented in hardware or software without occupying most of the available resources. Next to the delivered analysis of the system, the experimental demonstration on both FPGA and ESP32 Arduino platforms of chaotic synchronization between transmitter and receiver, included examples of applied encrypted communication in the case of consecutive picture and text transmissions.

The translation of emerging application concepts that exploit resistive random access memory (ReRAM) into large-scale practical systems requires realistic yet computationally efficient device models. Here, we present a ReRAM model, where device current-voltage characteristics and resistive switching rate are expressed as a function of: 1) bias voltage and 2) initial resistive state (RS). The model versatility is validated on detailed characterization data, for both filamentary valence change memory and nonfilamentary ReRAM technologies, where device resistance is swept across its operating range using multiple input voltage levels. Furthermore, the proposed model embodies a window function which features a simple mathematical form analytically describing RS response under constant bias voltage as extracted from physical device response data. Its Verilog-A implementation captures the ReRAM memory effect without requiring integration of the model state variable, making it suitable for fast and/or large-scale simulations and overall interoperable with current design tools.

We demonstrate a desktop platform which has the ability of modeling ReRAM TiO2samples in a highly automated manner. The system consists of a bespoke RRAM characterization instrument that hosts packaged RRAM devices and is operated via a PC. The system's python-based software includes a module that automatically applies strategically chosen sequences of pulses to a test device and then extracts the suitable parameter values for a resistive switching model from the elicited response.

In this paper a complete approach for timing and power modeling and characterization of the CMOS gates is proposed. At first, a simplified but still accurate transistor current model is proposed taking into account the nanoscale effects which have a countable effect on the circuit behavior. Using the expressions of the transistor current, the differential equation which describes the operation of the CMOS inverter is solved analytically and expressions for the output voltage and supply current and thus for propagation delay and the power consumption are derived. These expressions are parametric according the input signal slew, output load, transistor widths, supply voltage, temperature and process. Complex gates are replaced by equivalent inverters with similar behavior and the expressions developed for the inverter are employed. Parametric expressions are derived for the transistor widths of the equivalent inverters using a fitting procedure. Results for the NAND and NOR gates show that the proposed approach presents a sufficient accuracy with an average error in propagation delay at 5%.

Analysis of the operation of CMOS gates is a complicated procedure. These gates can be replaced by equivalent inverters and therefore the expressions for the inverters are used to determine the electrical characteristics of the gates. In this paper, the equivalent inverter approach for replacing CMOS gates is evaluated. The NAND gate is used for this evaluation. Parametric expressions are created to determine the transistors widths of the equivalent inverter. A systematic method is used for incorporating the parameter dependencies in the expressions. Results verify the accuracy of this approach.

In this paper, a new analytical model for describing the output waveform of the CMOS inverter for planar and FinFET nanoscale technologies, is introduced. A modified expression for the transistor current is adopted taken into account nano-scale effects like DIBL, CLM and NWE. The sub-threshold current of both transistors as well as their drain-to-bulk capacitances, which influence significantly the accuracy, are also considered. Results for 32nm planar and 20nm FinFET technologies validate the proposed model.

Hough Transform (HT) is a popular line detection algorithm in image processing and machine vision applications, favored for its tolerance to noise and partial occlusion. However, due to its computational complexity, software and hardware implementations for real-time video processing are usually limited to low resolutions and frame rates. We propose a novel architecture that exploits modern FPGA inherent parallelism capabilities, combined with efficient resource utilization and deep pipelining to enable real-time processing of high resolution, high frame rate videos.

This paper presents an FPGA-based machine vision implementation for flow detection on Lab-on-Chip (LoC) experiments. The proposed machine vision system is designed to provide real-time information to the LoC user about the state of the flows (flow coordinates and points of interest) as well as input to the LoC controller. It is uniquely designed to compensate noise in the input video originating from non ideal lighting conditions or LoC movement. This machine vision implementation achieves real time response for input videos of 1Mpixel resolution and frame-rates exceeding 60fps for microfluidic flows with a maximum speed of 20mm/sec.

Coupling reconfigurable hardware accelerators with processors is an effective way to meet the performance and flexibility required to cope with modern embedded applications. The ARISE framework provides a systematic approach to extend a processor once. It will thereafter support the coupling of arbitrary hardware accelerators. The accelerators can be coupled as coprocessors or functional units of the processor’s datapath, and therefore exploited as a hybrid, which includes both loose and tight computational models. This article presents a complete framework for developing applications on such hybrid reconfigurable ARISE machines. The framework integrates the automatic identification of custom instructions and the semiautomatic/profiling-driven identification of coprocessors supporting the hybrid computational model. Moreover, it supports a modular design approach where the software and the hardware modules are developed independently and later ported into any ARISE machine with reconfigurable technology. To evaluate efficiency, a set of benchmarks is implemented on an ARISE evaluation machine utilizing the proposed framework. In addition, the ARISE machine is compared against a well-established processor paradigm that utilizes reconfigurable accelerators following only the typical coprocessor approach. Experimental results prove that the framework can be used to exploit the hybrid computational model and achieve significant performance improvements over the typical coprocessor acceleration approach. Moreover, results demonstrate how the framework can be used to trade off performance, silicon area, and application development time.

ARISE introduces a systematic approach for extending once an embedded processor to support thereafter the coupling of an arbitrary number of custom computing units (CCUs). A CCU can be a hardwired or a reconfigurable unit, which can be utilized following a tight and/or loose model of computation. By selecting the appropriate model of computation for each part of the application, the complete application space is considered for acceleration, resulting in significant performance improvements. Also, ARISE offers modularity and scalability and is not restricted by the opcode space and operands limitation problems that exist in such type of machines. To support these features we introduce a machine organization that allows the cooperation of a processor and a set of CCUs. To control the CCUs we extend once the instruction set of the processor with eight instructions. To efficiently incorporate these features to an embedded processor, we propose a micro-architecture implementation that minimizes the control and communication overhead between the processor and the CCUs. To evaluate our proposal, we extended a MIPS processor with the ARISE infrastructure and implemented it on a Xilinx field-programmable gate array (FPGA). Implementation results, demonstrate that the timing model of the processor is not affected. Also, we implemented a set of benchmarks on the ARISE evaluation machine. Performance results prove significant improvements and reduced communication overhead compared to a typical coprocessor approach.

Looping operations impose a significant bottleneck in achieving better computational efficiency for embedded applications. In this paper, a novel zero-overhead loop controller (ZOLC) supporting arbitrary loop structures with multiple-entry and multiple-exit nodes is described and utilized to enhance embedded RISC processors. A graph formalism is introduced for representing the loop structure of application programs, which can assist in ZOLC code synthesis. Also, a portable description of a ZOLC component which can be exploited in the scope of register transfer level (RTL) synthesis for enabling its utilization is given in detail. This description is designed to be easily retargetable to single-issue RISC processors, requiring only minimal effort for this task. The ZOLC unit has been incorporated into different RISC processor models and research ASIPs at different abstraction levels (RTL VHDL and ArchC) to provide effective means for low-overhead looping without negative impact to the processor cycle time. Average performance improvements of 25.5 percent and 44 percent are feasible for a set of kernel benchmarks on an embedded RISC and an application-specific processor, respectively. A corresponding 10 percent speedup is achieved on the same RISC for a subset of MiBench applications, not necessarily featuring the examined performance-critical kernels.

By coupling a reconfigurable hardware to a standard processor, high levels of flexibility and adaptability are achieved. However, this approach requires modifications to the compiler of the processor to take into account reconfigurable aspects. In this paper, a development framework for a RISC processor with reconfigurable instruction set extensions is presented. The framework is fully automated, hiding all reconfigurable related issues from the user and can be used for both program and fine-tune the architecture at design time. We demonstrate the above issues using a set of benchmarks. Experimental results show an x2.9 average speedup in addition to potential energy reduction

Looping operations impose a significant bottleneck to achieving better computational efficiency for embedded applications. To confront this problem on embedded RISC processors, an architectural modification involving the integration of a zero-overhead loop controller (ZOLC) has been suggested, supporting arbitrary loop structures with multiple-entry and multiple-exit nodes. In this paper, a graph formalism is introduced for representing the loop structure of application programs, which can assist in ZOLC code synthesis. Also, a portable description of a ZOLC component is given in detail, which can be exploited in the scope of RTL synthesis, compiler optimizations or assembly level transformations for enabling its utilization. This description is designed to be easily retargetable to single-issue RISC processors, requiring only minimal effort for this task

A recent approach to platform-based design involves the use of extensible processors, offering architecture customization possibilities. Part of the designer responsibilities is the domain-specific extension of the baseline processor to fit customer requirements. Key issues of this process are the automated application analysis and candidate instruction identification/selection for implementation as application-specific functional units (AFUs). In this paper, a design approach that encapsulates automated workload characterization and instruction generation is utilized for extending processors to efficiently support embedded application sets. The method used for instruction generation is a highly parameterized adaptation of the MaxMISO technique, which allows for fast design space exploration. It is proven that only a small number of AFUs are needed in order to support the algorithms of interest (MPEG-4 encoding kernels) and that it is possible to achieve 2/spl times/ to 3.5/spl times/ performance improvements although further possibilities such as subword parallelization are not currently regarded.

The design of a novel embedded FPGA reconfigurable hardware architecture is introduced. The architecture features a number of circuit-level low-power techniques, since power consumption is considered a primary concern. Additionally, a complete set of tools facilitating implementation of applications on the proposed FPGA was presented, starting from an RTL description and producing the actual configuration bit stream. The designed full-custom FPGA is under fabrication in 0.18μm STM CMOS technology. The prototype supports partial and dynamic reconfiguration. The efficiency of the entire system (FPGA and tools) was proven by comparisons with commercial systems.

The program control unit of an embedded RISC processor is enhanced with a novel zero-overhead loop controller (ZOLC) supporting arbitrary loop structures with multiple-entry/exit nodes. The ZOLC has been incorporated to an open RISC processor core to evaluate the performance of the proposed unit for alternative configurations of the selected processor. It is proven that speed improvements of 8.4% to 48.2% are feasible for the used benchmarks.

Summary form only given. A complete system for the implementation of digital logic in a fine-grain reconfigurable platform is introduced. The system is composed of two parts: The fine-grain reconfigurable hardware platform (FPGA) on which the logic is implemented and the set of CAD tools for mapping logic to the FPGA platform. The novel energy-efficient FPGA architecture was designed and simulated in STM 0.18/spl mu/m CMOS technology. Concerning the tool flow, each tool can operate as a standalone program as well as part of a complete design framework, composed by existing and new tools.

Power savings that can be achieved by data-reuse decisions targeting at a custom memory hierarchy for multimedia applications executing on embedded cores are examined in this paper. Exploiting the temporal locality of memory accesses in data-intensive applications a set of data-reuse transformations on a typical motion estimation algorithm is determined. The aim is to reduce data related power consumption by moving background memory accesses to smaller foreground memories, which are less power costly. The impact of these transformations on power, performance and area is evaluated both for application specific circuits and general purpose processors. The number of data and instruction memory accesses is analytically calculated, enabling a fast exploration of the design space by varying algorithmic parameters.

Multimedia applications are characterized by an increased number of data transfer and storage operations due to real time requirements. Appropriate transformations can be applied at the algorithmic level to improve crucial implementation characteristics. The effect of the data-reuse transformations on power consumption, area and performance of multimedia applications realized on embedded cores is examined. As demonstrators, widely applicable video processing algorithmic kernels, namely the row-column decomposition DCT and its fast implementation found in MPEG-X, are used. Experimental results prove that significant improvements in power consumption can be achieved without performance degradation by the application of data-reuse transformations in combination with the use of a custom memory hierarchy.

A novel method for the accurate calculation of the transition activity at the nodes of a multiplier-accumulator (MAC) architecture implementing finite impulse response filters is proposed in this paper. The method is developed for input signals, which can be described by a stationary Gaussian process. The transition activity per bit of a signal word is modeled according to the dual-bit-type (DBT) model and it is described as a function of the signal statistics. An efficient analytical method has been developed for the determination of the signal statistics at each node of the MAC architecture. It is based on the mathematical formulation of the multiplexing in time of signal sequences with known statistics. The effect of the multiplexing mechanism on the breakpoints of the DBT model, which influences significantly the accuracy of the method, is also determined. Several experiments both with synthetic and real data have been conducted. The numerical results produced by the proposed models are in very good agreement with the measured values of the transition activity.

In this paper, a modeling technique for CMOS gates, based on the reduction of each gate to an equivalent inverter, is presented. The proposed method can be incorporated in existing timing simulators in order to improve their accuracy. The conducting and parasitic behavior of parallel and serially connected transistors is accurately analyzed and an equivalent transistor is extracted for each case, taking into account the actual operating conditions of each device in the structure. The proposed model incorporates short-channel effects, the influence of body effect and is developed for nonzero transition time inputs. The exact time point when the gate starts conducting is efficiently calculated improving significantly the accuracy of the method. A mapping algorithm for reducing every possible input pattern of a gate to an equivalent signal is introduced and the "weight" of each transistor position in the gate structure is extracted. Complex gates are treated by first mapping every possible structure to a NAND/NOR gate and then by collapsing this gate to an equivalent inverter. Results are validated by comparisons to SPICE and ILLIADS2 for three submicron technologies.

In this paper an accurate, analytical model for the evaluation of the CMOS inverter delay in the sub-micron regime, is presented. A detailed analysis of the inverter operation is provided which results in accurate expressions describing the output waveform. These analytical expressions are valid for all the inverter operation regions and input waveform slopes. They take into account the influences of the short-circuit current during switching, and the gate-to-drain coupling capacitance. The presented model shows clearly the influence of the inverter design characteristics, the load capacitance, and the slope of the input waveform driving the inverter on the propagation delay. The results are in excellent agreement with SPICE simulations.

The most common practice to model the transistor chain, as it appears in CMOS gates, is to collapse it to a single equivalent transistor. This method is analyzed and improvements are presented in this paper. Inherent shortcomings are removed and an effective transistor width is calculated taking into account the operating conditions of the structure, resulting in very good agreement with SPICE simulations. The actual time point when the chain starts conducting which influences significantly the accuracy of the model is also extracted. Finally, an algorithm to collapse every possible input pattern to a single input is presented.

Article Free Access Share on Accurate calculation of bit-level transition activity using word-level statistics and entropy function Authors: E. D. Kyriakis-Bitzaros Institute of Microelectronics, NCSR "Demokritos", 15310 Ag. Paraskevi Attikis, Greece Institute of Microelectronics, NCSR "Demokritos", 15310 Ag. Paraskevi Attikis, GreeceView Profile , S. Nikolaidis Department of Physics, University of Thessaloniki, 54006, Thessaloniki, Greece Department of Physics, University of Thessaloniki, 54006, Thessaloniki, GreeceView Profile , A. Tatsaki Silicon Graphics, Computer Systems, 2011 N. Shoreline Bird, Mountain View, CA Silicon Graphics, Computer Systems, 2011 N. Shoreline Bird, Mountain View, CAView Profile Authors Info & Claims ICCAD '98: Proceedings of the 1998 IEEE/ACM international conference on Computer-aided designNovember 1998 Pages 607–610https://doi.org/10.1145/288548.289095Online:01 November 1998Publication History 2citation179DownloadsMetricsTotal Citations2Total Downloads179Last 12 Months5Last 6 weeks2 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

This paper presents an accurate model for the evaluation of the CMOS short-circuit power dissipation for short-channel devices, on the basis of a CMOS inverter. The improvement of the proposed approach against previous works is due to the new derived, accurate, analytical expressions for the inverter output waveform which include for the first time the influences of both transistor currents, and the gate-to-drain coupling capacitance. The results produced by she suggested model show good agreement with SPICE simulations.