In this paper, we study a mask-cost-aware routing problem for engineering change order (ECO). By taking into account old routes for possible reuse, we present an approach for the problem. Encouraging experimental results are reported to demonstrate the effectiveness of our approach.

Most traffic accidents resulted from distraction, inattention to surrounding cars, and driving fatigue. In order to protect drivers, a real-time lane-detection and front-vehicle distance measurement system that uses a mounted camera inside a vehicle has been designed for safe driving. For lane detection, the lane-boundary information is derived from the fan-scanning-detection method. The system calculates the departure degree according to the angular relationship of the boundaries and sends a suitable warning signal to drivers. For front-vehicle distance measurement, we use the front vehicle's shadow underneath it to identify the position of the front vehicle. The real distance is estimated by the use of the functional neurofuzzy network. The experimental results show that the system works successfully in real-time environment.

Considering the physical layout, a comprehensive TCAM test scheme divides TCAM test into test for TCAM core and test for peripheral circuit. Besides, it schedules the existing test algorithms to develop an optimized test algorithm.

Content addressable memories (CAMs) are widely used in digital systems. A test algorithm for CAMs must be able to cover the random access memory (RAM) faults and comparison faults. However, CAM circuits are usually customized for different products, so there are no standard tests, i.e., tests should be adapted to a specific design manufactured using specific technology. This paper presents a fault simulator, called CAM Evaluation tooL (CAMEL), for the evaluation of fault coverage of CAM test algorithms. It supports five common functional outputs, i.e., Data I/O, hit, multi-hit, matchout, and priority address for various CAM specifications. Since coupling fault simulation dominates the efficiency of a memory fault simulator, a concept of observability is proposed to simplify the coupling fault behavior. By exploiting the observability, a compression technique is also proposed to speed up the fault simulation and reduce memory usage. CAMEL can support both RAM faults and comparison faults. We have demonstrated the CAMEL using widely-used March tests and CAM tests. Simulation results show that the CAMEL can evaluate the fault coverage of tests accurately and efficiently.

With the advance of VLSI technology, the capacity and density of memories is rapidly growing. The yield improvement and testing issues have become the most critical challenges for memory manufacturing. Conventionally, redundancies are applied so that the faulty cells can be repairable. Redundancy analysis using external memory testers is becoming inefficient as the chip density continues to grow, especially for the system chip with large embedded memories. This paper presents three redundancy analysis algorithms which can be implemented on-chip. Among them, two are based on the local-bitmap idea: the local repair-most approach is efficient for a general spare architecture, and the local optimization approach has the best repair rate. The essential spare pivoting technique is proposed to reduce the control complexity. Furthermore, a simulator has been developed for evaluating the repair efficiency of different algorithms. It is also used for determining certain important parameters in redundancy design. The redundancy analysis circuit can easily be integrated with the built-in self-test circuit.

Abstract To implement 4G wireless that should deliver a much higher data‐rate than that possible in the current 3G systems, development of innovative air‐link technologies is the key. This article reviews our on‐going research activities in the design of ‘isotropic air‐interface technologies’ capable of substantially improving air‐link performance of a CDMA wireless system. To enable bidirectional high‐speed data transmission in the future 4G systems, the problem associated with incompatible up‐ and down‐link performance in 2–3G systems has to be addressed. The importance of the issue becomes even more evident due to the fact that the future wireless needs to support ‘mobile server’ applications, where a mobile terminal may act as a data source such that up‐link traffic can possibly exceed that in down‐link. In this article, two alternative methods enabling isotropic air‐interface will be discussed, either using ‘isotropic spreading techniques’ that ensure a homogeneous link‐performance regardless of its operation mode (synchronous or asynchronous), or relying on a precision up‐link synchronization control techniques to pave a way for successful application of orthogonal codes in up‐link channels, which otherwise are asynchronous and destroy the ‘orthogonality’ amongst the codes. The isotropic spreading techniques can minimize multiple access interference (MAI) and multipath‐interference (MI), the prevalent impairing effects in the current 2–3G systems. This article will introduce a promising complete complementary CC/DS‐CDMA scheme based on isotropic spreading techniques, which carries several extremely attractive properties such as MAI‐free, MI‐free, near–far effect resistance and low hardware complexity. The performance of the proposed CC/DS‐CDMA scheme is limited only by noise. To implement up‐link synchronization control, smart antenna and GPS‐based techniques play an important role and a working example based on TD‐SCDMA standard will be illustrated. Finally, we will also discuss the TDD techniques and its significance to implement isotropic air‐interface technologies for the future 4G systems. Copyright © 2003 John Wiley & Sons, Ltd.

The size and density of semiconductor memories is rapidly growing, making them increasingly harder to test. New fault models and test algorithms have been continuously proposed to cover defects and failures of modern memory chips and cores. However, software tool support for automating the memory test development procedure is still insufficient. For this purpose, we have developed a fault simulator (called RAMSES) and a test algorithm generator (called TAGS) for random-access memories (RAMs). In this paper, we present the algorithms and other details of RAMSES and TAGS and the experimental results of these tools on various memory architectures and configurations. We show that efficient test algorithms can be generated automatically for bit-oriented memories, word-oriented memories, and multiport memories, with 100% coverage of the given typical RAM faults.

Testing and diagnosis are important issues in system-on-chip (SoC) development, as more and more embedded cores are being integrated into the chips. In this paper we propose a built-in self-test (BIST) and self-diagnosis (BISD) scheme for embedded SRAMs, suitable for SoC applications. It supports manufacturing test as well as diagnosis for design verification and yield improvement. With low hardware cost, our memory BISD approach can handle various types of SRAM, including pipelined, multi-port, and multi-clock architectures. In addition, a test scheduling methodology and a BISD compiler are also implemented, which reduce the testing time as well as test development time.

The paper presents a simulation-based test algorithm generation and test scheduling methodology for multi-port memories. The purpose is to minimize the testing time while keeping the test algorithm in a simple and regular format for easy test generation, fault diagnosis, and built-in self-test (BIST) circuit implementation. Conventional functional fault models are used to generate tests covering most defects. In addition, multi-port specific defects are covered using structural fault models. Port-scheduling is introduced to take advantage of the inherent parallelism among different ports. Experimental results for commonly used multi-port memories, including dual-port, four-port, and $n$-read-1-write memories, have been obtained, showing that efficient test algorithms can be generated and scheduled to meet different test bandwidth constraints. Moreover, memories with more ports benefit more with respect to testing time.

Embedded memory test and diagnosis is becoming an important issue in system-on-chip (SOC) development. Direct access of the memory cores from the limited number of I/O pins is usually not feasible. Built-in self-diagnosis (BISD), which include built-in self-test (BIST), is rapidly becoming the most acceptable solution. We propose a BISD design and a fault diagnosis system for embedded SRAM. It supports manufacturing test as well as diagnosis for design verification and yield improvement. The proposed BISD circuit is on-line programmable for its March test algorithms. Test chips have been designed and implemented. Our experimental results show that the BISD hardware overhead is about 2.4% for a typical 128 Kb SRAM and only 0.65% for a 2 Mb SRAM.

We present an error catch and analysis (ECA) system for semiconductor memories. The system consists of a test algorithm generator called TAGS, a fault simulator called RAMSES, and an error analyzer (ERA). We use TAGS to generate a set of test algorithms of different lengths and diagnostic resolutions for the memory under test, and use RAMSES to generate the March dictionary for each test algorithm. With the March dictionaries, ERA is able to support March algorithms for easy diagnosis of faulty RAMs. Legacy test algorithms also can be reused. When integrated with a RAM tester, our ECA system can generate RAM bitmaps that are similar to the RAM layout. The bitmaps provide detail information about the error locations and faults causing the errors. Based on the information, diagnosis of the RAM chips for yield and reliability improvement can be done more easily.

Although there are well known test algorithms that have been used by the industry for years for testing semiconductor random-access memories (RAMs), systematic evaluation of their effectiveness and efficiency has been a difficult job. In the past, it was mainly done manually by proving a certain algorithm can detect a certain type of fault. As memory technology keeps innovating, the growing complexity of the memories and number of fault types that need to be covered will require more effective and efficient test algorithms to be discovered in much shorter time. A systematic approach for developing and evaluating memory test algorithms is thus desired. We propose such an approach here: test algorithm generation by simulation (TAGS), which generates and optimizes test algorithms, given a test time budget. Experimental results show that the algorithms generated by TAGS are more efficient than the traditional test algorithms. Using TAGS, a series of test algorithms with a detailed list of faults covered by each algorithm can be generated, providing easy trade-off between test time and fault coverage.

Field Programmable Gate Arrays (FPGAs) are an increasingly popular choice for fast prototyping and for products whose time to market is relatively short. Testing FPGAs before programming them is thus becoming a major concern to the manufacturers as well as the users. In this paper we propose a universal test for the interconnects of typical dynamic reconfigurable FPGAs. The proposed test configurations and corresponding test patterns for the Xilinx XC6200 FPGAs are shown to cover all interconnect faults. In our test, the total number of test configurations is only 7, which is independent of the FPGA size. The test time for XC6216 is less than 5 ms.