Three-dimensional (3D) scene rendering is implemented in the form of a pipeline in graphics processing units (GPUs). In different stages of the pipeline, different types of data get accessed. These include, for instance, vertex, depth, stencil, render target (same as pixel color), and texture sampler data. The GPUs traditionally include small caches for vertex, render target, depth, and stencil data as well as multi-level caches for the texture sampler units. Recent introduction of reasonably large last-level caches (LLCs) shared among these data streams in discrete as well as integrated graphics hardware architectures has opened up new opportunities for improving 3D rendering. The GPUs equipped with such large LLCs can enjoy far-flung intra- and inter-stream reuses. However, there is no comprehensive study that can help graphics cache architects understand how to effectively manage a large multi-megabyte LLC shared between different 3D graphics streams.

We present a methodology that can analyze the effect of process variations without requiring the repeated simulations of a Monte Carlo type method. A graph theoretic procedure is described to obtain an explicit differential equation from the differential algebraic equations modeling a circuit netlist. With this explicit form, Taylor series polynomials are used to represent the system variables. The non-constant process parameters are represented as intervals, the Taylor series expansion is used to perform interval computations to generate bounds for the system variables. Methods are discussed to prevent blow-up of intervals during the time marching method.