This paper presents the design and simulations of a UCIe transmitter driver in 28 nm FDSOI technology. The design targets the Advanced Package UCIe specification, which is characterized by high bandwidth density and good energy efficiency. The circuit is optimized for power consumption, duty cycle distortion and jitter, taking into account the reference UCIe channel model. The 8 Gbps non-return-to-zero (NRZ) TX driver design achieves 663 fs of jitter without supply noise and 14.6 ps with 80 mVpp supply noise over PVT, after duty-cycle distortion calibration. The energy consumption of the circuit is$320.3 \text{fJ} / \text{bit}$in the high-voltage (HV) mode and$193.3 \text{fJ} /$bit in the low-voltage (LV) mode. The output resistance is below 30Ω, and according to the package model simulations, it has a negligible effect on jitter on the receiving side.

As semiconductor technologies scale into advanced sub-micron and FinFET nodes, layout complexity continues to grow. Modern analog and mixed-signal (AMS) designs use many metal layers, dense routing, and tight device-level constraints to meet demanding requirements. In these layouts, structures like floating shapes create serious risks. They can introduce parasitic coupling, affect simulation accuracy, and increase Electrostatic Discharge (ESD) sensitivity etc. Floating-shape problems are well known in semiconductor layout. There is no widely adopted automated method for detecting these problems. Existing research focuses primarily on modelling and analysis rather than automated detection. This work presents a floating-shape detection software implemented in Cadence Pegasus using Pegasus Verification Language (PVL). The design method repurposes the ANTENNA rule to trace connectivity through stacked metals, device terminals and labels. Consequently, it provides a unique framework to address the problem of floating shapes.

This paper explains the background of the well-edge proximity effect (WPE) and sums up its impact on pMOS threshold voltage$(V_{th})$in the following CMOS technologies: 65nm (bulk), 40nm (bulk) from two different vendors, 28nm (bulk and FDSOI) and 16nm (FinFET). The results clearly show that WPE cannot be ignored during layout design for any of presented technology. Fortunately, the effect of well-edge proximity is essential at 1 μm or shorter distances. At longer distances its impact decreases almost to zero. In 40nm technology it can change threshold voltage even by 33 % for IO devices while at 16nm the change will be just 1.87%. Although the technologies are varied in transistor length and process of fabrication the WPE effect remains present.

This paper presents a Differential Amplifier architecture realizing a Physical Unclonable Function. The differential structure has been chosen to improve robustness of the PUF. The proposed circuit achieves temperature-dependent reliability equal to 94.49% and voltage supply-dependent reliability as high as 99.33%. The PUF uniqueness is 49.24% with a standard deviation equal to 0.0442.

This paper presents the design of an oscillator-based true random number generator. The operation of the presented TRNG architecture is based on sampling a high-frequency oscillator output with a clock generated by a low-frequency noisy oscillator. The recycling folded cascode architecture was used for low power noise amplifier. A new method to achieve higher jitter in the low frequency oscillator is presented. The bit rate of the designed TRNG is 1.02 Mb/s. The circuit power consumption is 67 μW. The results of the simulations and statistical tests of the designed random number generator are also presented in this paper.

The paper is a contribution to the 50th anniversary celebration of the International Test Conference (ITC) and its Global Test Forum (GTF), which honors the geographic breadth of the test community and highlights the global reach of ITC during the past 50 years. It covers the past, present, and future of the International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), a symposium which belongs to prominent test technology related events initiated and supported by the ITC.

This paper presents the application of FD-SOI body-biasing technique to improve robustness against PVT of an LC-tank voltage controlled oscillator (VCO). Designed VCO operates at 2.4 GHz ISM band and achieves phase noise level below -109.6 dBc/Hz. Power consumption equals 2.805 mW in the worst case. 28 nm FD-SOI process has been used.

Analog front-end for precise temperature measurement of a human body has been presented. The discussed analog front-end (AFE) contains a new temperature calibration technique based on on-chip resistor. The described calibration method allows to obtain very high accuracy, even 0.1 °C, in very wide range of an operating temperature of an integrated circuit. The AFE consists of a bandgap current reference, a precision current source, a programmable gain amplifier, a voltage source proportional to absolute temperature and on-chip temperature calibration resistor. The presented analog front-end consumes no more than 180 uW and was designed and manufactured in UMC CMOS 130 nm technology. All data presented in the article were obtained from measurements. Measurements were taken using manual wafer prober with climate control microchamber, at temperature range from -40 °C to 125 °C.

The paper presents an Integer-N phase locked loop (PLL) for Bluetooth receiver implemented in CMOS 130 nm technology. The presented phase locked loop consists of an LC quadrature voltage controlled oscillator with capacitor bank, a tri-state phase-frequency detector with charge pump, a third order passive filter and a programmable divider. The PLL has a supply voltage of 1.2 V and dissipates 2.4 mW. The output frequency range of the phase locked loop is from 2.2 GHz to 2.8 GHz and phase noise is equal -124 dBm/Hz at 3 MHz from carrier frequency.

An analog front-end, with a new temperature calibration method, for an accurate temperature measurement of a human body has been presented. The discussed AFE consists of a current reference, a precision current source, a programmable gain amplifier, a voltage source proportional to absolute temperature and on-chip temperature calibration resistor. Human body temperature can be measured in the range from +25 °C to +45 °C at the operating temperature of an IC in the range from -40 °C to +125 °C with 0.1 °C precision. The presented analog front-end consumes no more than 180 uW and was designed in UMC CMOS 130 nm technology.

The BioSoC is a highly integrated SoC that consists of analog front-ends, analog to digital converters and a 32-bit microcontroller - Adelite. The designed IC allows for dynamic acquisition and processing of the most important human physiological parameters. The provided analog interfaces to external electrodes and sensors allow measurement of electrocardiograms (ECG), electromyograms (EMG), skin temperature and resistance, and respiration rate (RR). After analog processing signals are sampled and digitized in analog-to-digital converters they can be further processed in a 32-bit microcontroller Adelite. The clock frequency of the microprocessor core is configurable from 32 kHz up to 16 MHz. The microcontroller is equipped with many digital interfaces and peripherals, such as 2×UART and 2×SPI with DMA channels, 16 GPIOs and 5 timers along with RTC. The BioSoC makes it possible to build highly integrated devices with rich functionalities in the area of telemedicine that respond to the growing demand for portable health monitoring. The BioSoC was designed and fabricated in UMC CMOS 130 nm technology process and occupies the area of 25mm2.

Experimental results of a fully integrated low ripple charge pump voltage converter are presented. The pump is a current mode voltage doubler with a novel parasitic capacitance precharge mechanism for output voltage ripple reduction. A prototype of the pump was designed and fabricated in 130 nm CMOS process. The pump supplied with 1.2 V delivers 1.5 V on its output. Despite reducing the size of the filtering capacitor (down to 5.2 % of the "flying" capacitor), the ripple level is 50 mV.

Recently, we are witnessing a rapid development in many fields of science, including medicine and healthcare. One of the visible results of such progress is an increasing average length of human life and the process of population aging. Advancements in sensor technology and wireless communication contributed to the development of the out-of-hospital health-monitoring concept [1]. One of its main advantages is the opportunity to provide remote healthcare, which enables extended independent living at home and improvement of quality of live. This paper presents the ADELITE micro controller for biomedical applications. While developed biomedical analog front-end of ADELITE micro controller is currently under measurements, results presented in the paper refer to the first implementation of the digital part of the developed micro controller. The long term target of the design is a full system-on-chip implementation. The presented prototype of ADELITE micro controller was fabricated with UMC CMOS 130 nm technology. The design occupies the area of 1.5 mm2and consumes only 100 μA/MHz. The ADELITE processing power is 0.95 DMIPS/MHz and 1.89 Core Mark/MHz with 16 MHz of clock frequency.

This paper presents a verification architecture of the Bluetooth Low Energy Link Layer Controller. The tested controller is a hardware implementation of the lower layers, described in the Bluetooth Low Energy Specification. The designed test bench uses a UVM methodology and constrained random verification techniques to meet the expected functional coverage metrics.

This paper presents the architecture of an improved charge pump high voltage converter. The converter's output voltage ripple has been reduced. Novel concepts were tested with the usage of 0.13 um CMOS technology simulations. The proposed charge pump input voltage is 1.2 V. The pump output voltage level is 6.69 V. The output voltage ripple amplitude is 16 mV.

In this paper an intermediate frequency filter calibration method for radio frequency receivers has been presented. The method allows calibrating bandwidth of low-pass filters and center frequency of band-pass filters. Most of the calibration process is done in the digital domain and only one analogue buffer and one multiplexer are necessary. The presented method calibrates directly the filter that is actually in the signal path. The benefit of this method is that no filter replica is needed and only a small part of the calibration circuitry has to be placed near the filter. Moreover, problems with mismatch between the filter replica and the actual filter are avoided. The method was implemented as a part of the multi-standard GNSS receiver implemented in UMC 130 nm CMOS technology.

Providing low power consumption, high throughput and flexible solution is a challenge during designing process of a mobile software defined radio (SDR) system. The need for simple software generation using common programming tools becomes also a very significant factor. The paper presents the design and implementation of a chip multithreading general-purpose processor core (GPP), as the first step towards designing a flexible and programmer friendly SDR processor platform. Software tools developed for the hardware are described. The future work will be focused on designing tightly-coupled coprocessor extensions (TCC) for an application specific digital signal processing (DSP) purposes. AGATE processor system is described in form of a highly configurable library using Verilog language. The concept verification process was performed on the Xilinx Virtex-6 ML605 FPGA evaluation board. The maximum achieved frequency for the 8-thread processor is 190 MHz. Gate level simulation along with Value Change Dump (VCD) power estimation analysis were performed using three CMOS technologies: 130 nm, 90 nm and 65 nm. AGATE is capable of performing up to 0.72 DMIPS/MHz/thread with the maximum frequency of over 700 MHz and the power consumption of about 3 mW/core using 65 nm process.

In this paper a low-voltage LC voltage-controlled oscillator (VCO) design automation tool has been presented. The tool is based on design methodology, which takes under consideration trade-offs between power consumption, phase noise and tuning range. NMOS only architecture is considered because of its capability to work with low supply voltages. One of the goals, while creating the tool, was to make it technology independent. This was achieved by creating SKILL scripts that allows fast configuration of design library for specified technology. Trade-offs between power consumption, phase noise and tuning range are analyzed and based on them design flow has been proposed. Finally two design examples in 90 and 130 nm CMOS technology have been presented.

In this paper a 5Gb/s equalizer has been presented. It is designed to operate within USB 3.0 transceiver and compensates for frequency dependent losses introduced by transmission channel. For the reference signal, the clock and data recovery circuit has been used. This approach allowed to minimize the equalizer components. Critical equalizer building blocks have been implemented in GLOBALFOUNDRIES 65 nm Low Power CMOS technology. Other blocks are modeled in hardware description language. Mixed-signal system simulation results show full functionality of the proposed solution.

A reistorless current reference source, e.g. for fast communication interfaces, has been described. Addition of currents with opposite temperature coefficient (PTC and NTC) and body effect have been used to temperature compensation. Cascode structures have been used to improve the power supply rejection ratio. The reference current source has been designed in a GLOBALFOUNDRIES 65 nm technology. The presented circuit achieves 55 ppm/°C temperature coefficient over range of −40 °C to 125 °C. Reference current susceptibility to process parameters variation is ±3 %. The power supply rejection ratio without any filtering capacitor at 100 Hz and 10 MHz is lower than −127 dB and −103 dB, respectively.

In this paper low-voltage LC voltage-controlled oscillator (VCO) with low sensitivity to process, voltage and temperature (PVT) variations has been presented. VCO operates at 3.2 GHz and its output signal frequency is divided by 2 in quadrature divider to generate quadrature signals at 1.6 GHz. The NMOS cross-coupled architecture, proper varactor biasing, tuning curve linearization technique and switched-capacitor (SC) current source were used to reduce the sensitivity to PVT variations. The LC-VCO was designed with the usage of Low-Leakage UMC 90 nm CMOS technology. It achieves phase noise of -117 dBc/Hz at 1 MHz offset and draws 1.2 mA (VCO+Quadrature Divider) from 1.2 V supply voltage.

In this paper PLL Design tool, created in Matlab from MathWorks, has been presented. The tool allows to analyze loop stability and phase noise of PLL, based on phase-locked loop linear model. Fast evaluation of loop filter components values for popular passive and active filters is possible. The created tool allows to analyze PLL parameters, like loop filter components values, VCO gain and charge pump current variations impact on loop stability and phase-noise. Algorithm for phase-noise calculation, based on transient PLL simulation, has also been implemented. Thanks to these features the created tool is a valuable aid for PLL designer on all design steps.

In this paper a comparison of two low noise amplifiers (LNAs) designed in two 90 nm CMOS technologies (so called A and B) has been made. For each technology two LNA topologies were simulated: inductively degenerated cascode (LC), which achieves high gain and low noise figure (NF), and folded cascode (FC), which can work with low supply voltage. These amplifiers were designed for a GPS/Galileo receiver. Chosen circuits demonstrate gains of 16.42 dB, 17.27 dB, 14.51 dB and 14.41 dB, consuming currents 2.492 mA, 3.093 mA, 2.834 mA and 4.609 mA with NFs equal to 1.881 dB, 1.914 dB, 2.345 dB and 2.427 dB for LC and FC architecture in A and B technologies respectively. For all amplifiers the supply voltage is 0.6 V.

In this paper, two topologies of CMOS low noise amplifiers (LNAs) have been simulated. The inductively degenerated cascode (LC), which achieves high gain and low noise figure (NF), and folded cascode (FC), which can work with ultra low supply voltage, were considered. LNAs were optimized for a GPS/Galileo receiver using UMC 90 nm CMOS technology. Chosen circuits demonstrate a gain of 16.42 dB and 17.27 dB, consuming current 2.492 mA and 3.093 mA, showing NF 1.881 dB and 1.914 dB, third order input interception point (IIP3) -14.99 dBm and -13.3 dBm, input referred 1-dB compression point (Pin-1) -29 dBm and -29.47 dBm for inductively degenerated cascode and folded cascode respectively. Both input return loss (S11) and output return loss (S22) are below -40 dB. For these circuits supply voltage is 0.6 V and die area equals 0.33 mm2.

MDCT is the basic processing component for high quality audio compression. It is also the most computationally intensive operation in the vast majority of audio compression standards. Mostly used audio standard for audio compression is still MP3. This paper presents new implementations of five MDCT / IMDCT architectures with different parallelization levels for MP3. Implementation utilize UMC 90 nm CMOS technology. Design was optimized for low power applications. Low power libraries and clock gating technique were used for power reduction. All IP cores are capable of computing forward and backward MDCT and this feature makes them universal in multimedia SoCs for accelerating the MP3 audio compression/decompression.

Low power consumption and high-performance are two main directions in the development of modern microprocessor architectures. In general they are two excluding branches of System-on-Chip (SoC) evolution. The paper presents the methodology of enhancing LEON3 processor IP core with superscalar abilities for low-power or high-performance systems. In comparison with the original LEON3 IP core, the new one may execute up to two instructions per cycle with only one third increase in area occupation. The Enhanced LEON3 IP core was synthesized using UMC 90 nm CMOS technology.

Current paper proposes a new hierarchical approach to defect-oriented testing of CMOS circuits. The method is based on critical area extraction for identifying the possible shorted pairs of nets on the basis of the chip layout information, combined with logic-level test pattern generation. The novel contributions of the paper are a new bridging fault simulator and a test pattern generator, which are able to handle defects creating feedbacks into the circuit. As a preprocessing step, a combined stuck-at test set from two different test pattern generators implementing alternative strategies (pseudorandom and deterministic) were created. Nevertheless, many short defects were not covered by this extended stuck-at approach. Analyses carried out in this paper show that the stuck-at tests are not covering up to 4% of the shorts (both testable and untestable). The test coverage (fault efficiency) can be increased by the new generator by up to 0.4% in comparison to full stuck-at test. Layout analysis for a set of benchmarks has been performed. The experiments indicate how the number of bridging faults of non-zero probability is dependent on the circuit size.

This work shows a new concept to extend the hierarchical approach of standard-cell circuit design into the area of defect-oriented test pattern generation. For this purpose test patterns to detect shorts for each standard-cell are created separately. A new defect-oriented test generator (DOT) is using these single cell test pattern lists to create test patterns for the complete circuit. Additionally, test patterns for the routing network will be created. This work targets mainly shorts, but also other defects can be treated in a similar way. In order to generate tests only for relevant combinations of shorted nodes, the critical area for both the cells and the routing network is determined separately and the probability for each short is computed. Shorts inside the routing network can show sequential behaviour. The proposed test pattern generator is also able to find tests for such kind of defects. As the effort to test sequential defects can vary from short to short, a new testability analysis is presented. Based on this analysis a redesign of the circuit layout is proposed. This "layout for testability" approach is therefore a defect oriented equivalent for "design for testability" methods.

A method is proposed for combinational deterministic test pattern generation using a uniform functional fault model for combinational circuits. This includes an approach, which allows to find the types of faults that may occur in a real circuit and to determine their probabilities. Additionally, a defect-oriented deterministic test generation tool was developed (DOT), and the experimental data obtained by the tool for ISCAS'85 benchmarks are presented. It was shown that 100% stuck-at fault tests covered only about 80-90% physical defects. The main feature of the new tool is its ability to reach 100% defect efficiency for the given set of defects by proving the redundancy of not detected defects. An interesting conclusion of the experiments is also that up to 25% of the defects cannot be covered by any voltage test approaches.

This paper describes an algorithm for the extraction of the critical area for opens. The presented algorithm allows for the analysis of industrial size ICs with non-Manhattan geometry. Illustrative examples of the proposed algorithm, implemented by using design rule checker operations, are presented. It is shown that the extraction of the critical area for realistic size VLSI circuits designs can be done in an acceptable time.

Owing to rapid changes of IC technologies, traditionaldesign rule checking is becoming inadequate to assure satisfactorylevels of IC manufacturability. This paper describes a newcomputer supported design analysis environment that improvesthe efficiency of manufacturability assessment of new products.This environment, called MAPEX 2, is described in the paperalong with some of its key procedures and algorithms. Illustrationsof MAPEX 2 applications and performance figures are provided as well.