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Tohru Moto-Oka

dblp:71/6241 · DBLP profile ↗
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5ranked-venue papers
2as first author
0since 2021 · last 1986
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 2 first-authorSoftware engineering, systems software and programming languages · 2 · 1 first-authorDatabases, data management, data science and information retrieval · 1Theory of computation · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Databases, data mining, and information retrieval
1 paper
Indexing and storage engines · 50% Data mining · 50%
Computer architecture, parallel and distributed computing, and storage systems
4 papers
Parallel and multicore computing · 38% Performance modeling and evaluation · 30% Electronic design automation · 25%

Topics — the 12 heaviest of 12, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Data mining › clustering
adaptive clustering
0.011985
Algorithm and Performance Evaluation of Adaptive Multidimensional Clustering Technique · SIGMOD Conference 1985
Indexing and storage engines
multidimensional clustering
0.011985
Algorithm and Performance Evaluation of Adaptive Multidimensional Clustering Technique · SIGMOD Conference 1985
Parallel and multicore computing › parallel computing
fifth generation computer system
0.011983
Overview to the Fifth Generation Computer System Project · ISCA 1983
Performance modeling and evaluation
benchmarking
0.011985
Algorithm and Performance Evaluation of Adaptive Multidimensional Clustering Technique · SIGMOD Conference 1985
Performance modeling and evaluation
workload characterization
0.011985
Algorithm and Performance Evaluation of Adaptive Multidimensional Clustering Technique · SIGMOD Conference 1985
Electronic design automation › design automation tools
logic design system
0.011975
Logic design system in Japan · DAC 1975
Electronic design automation
logic synthesis
0.011975
Logic design system in Japan · DAC 1975
Integrated circuit design
digital circuit design
0.011960
Esaki Diode High-Speed Logical Circuits · IRE Trans. Electron. Comput. 1960
Integrated circuit design › digital circuit design › logic design
logic circuits
0.011960
Esaki Diode High-Speed Logical Circuits · IRE Trans. Electron. Comput. 1960
Integrated circuit design › digital circuit design › logic families
tunnel diode logic circuits
0.011960
Esaki Diode High-Speed Logical Circuits · IRE Trans. Electron. Comput. 1960
Memory systems
delay-line memory
0.011960
Esaki Diode High-Speed Logical Circuits · IRE Trans. Electron. Comput. 1960
Memory systems › random-access memory
dynamic memory
0.011960
Esaki Diode High-Speed Logical Circuits · IRE Trans. Electron. Comput. 1960

Methods — techniques the papers use, named apart from their topics

performance evaluation · 0.0subharmonic oscillator · 0.0majority logic · 0.0
YearPublicationVenuePosition
1986 Tokio: Logic Programming Language Based on Temporal Logic and its Compilation to Prolog
Shinji Kono, Hidehiko Tanaka, Tohru Moto-Oka
ICLP4
1985 Algorithm and Performance Evaluation of Adaptive Multidimensional Clustering Technique
abstract
Article Free Access Share on Algorithm and performance evaluation of adaptive multidimensional clustering technique Authors: Shinya Fushimi Department of Electrical Engineering, University of Tokyo Department of Electrical Engineering, University of TokyoView Profile , Masaru Kitsuregawa Institute of Industrial Science, University of Tokyo Institute of Industrial Science, University of TokyoView Profile , Masaya Nakayama Department of Electrical Engineering, University of Tokyo Department of Electrical Engineering, University of TokyoView Profile , Hidehiko Tanaka Department of Electrical Engineering, University of Tokyo Department of Electrical Engineering, University of TokyoView Profile , Tohru Moto-oka Department of Electrical Engineering, University of Tokyo Department of Electrical Engineering, University of TokyoView Profile Authors Info & Claims SIGMOD '85: Proceedings of the 1985 ACM SIGMOD international conference on Management of dataMay 1985Pages 308–318https://doi.org/10.1145/318898.318928Published:01 May 1985Publication History 8citation361DownloadsMetricsTotal Citations8Total Downloads361Last 12 Months14Last 6 weeks5 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF
Shinya Fushimi, Masaru Kitsuregawa, Masaya Nakayama, Hidehiko Tanaka, Tohru Moto-Oka
SIGMOD Conference5
1983 Overview to the Fifth Generation Computer System Project
abstract
Computers which have high performances for non-numeric data processing should be developed in order to satisfy and expand new applications which will become predominant fields in information processing of the 1990s.
Tohru Moto-Oka
ISCA1
1975 Logic design system in Japan
Tohru Moto-Oka, Tadashi Kurachi, Tsutomu Shiino, Masakatsu Sugimoto
DAC1
1960 Esaki Diode High-Speed Logical Circuits
abstract
Logical circuits using Esaki diodes, and which are based on a principle similar to parametron (subharmonic oscillator element) circuits, are described. Two diodes are used in series to form a basic element called a twin, and a binary digit is represented by the polarity of the potential induced at the middle point of the twin, which is controlled by the majority of input signals applied to the middle point. Unilateral transmission of information in circuits consisting of cascaded twins is achieved by dividing the twins into three groups and by energizing each group one after another in a cyclic manner. Experimental results with the clock frequency as high as 30 mc are reported. Also, a delay-line dynamic memory and a nondestructive memory in matrix form are discussed.
Eiichi Goto, Kenro Murata, Kisaburo Nakazawa, Keisuke Nakagawa, Tohru Moto-Oka, Yasushi Miatsu-Oka, Yoshihiro Ishibashi, Haruhisa Ishida, Takashi Soma, Eiiti Wada
IRE Trans. Electron. Comput.5