This paper proposes a power/area efficient method for realizing a class of downsampled floating tap decision feedback equalization (DFE) architectures for serial links. The architectures offer significant complexity and power reduction over a standard floating tap DFE architecture with minimal performance loss. A shift register multi-phase clock based design in 28 nm CMOS is implemented for operation at 28.05 Gb/s. At 28.05 Gb/s, the designed downsampled architecture dissipates only 67% of the power of the corresponding standard architecture operating at 17 Gb/s. At the lower 17 Gb/s speed, the downsampled architecture dissipates only 45% of the power of the standard architecture.

This paper analyzes the performance of a class of decimated clock data recovery (CDR) architectures for serial links. Jitter tolerance is obtained analytically following a derivation of the phase detector (PD) gain for sinusoidal jitter and a derivation of the CDR linear transfer function. A methodology is proposed to perform the analysis iteratively with a dynamic PD gain. The analysis is shown to correlate well with time step simulation results which simulate the non-linear behavior of the PD. Analysis results are presented for multiple decimation factors.

This paper proposes a class of downsampled floating tap decision feedback equalization (DFE) architectures based on downsampling of the floating tap positions. The architectures offer significant complexity and power reduction compared with a standard floating tap DFE architecture with minimal loss in performance. Simulation results with realistic channel models are used to validate the performance of these architectures.

This paper proposes adaptation algorithms for adapting a class of practical continuous time equalizer architectures. Gradient equations used to adapt the equalizer are derived based on impulse response weights related to the equalizer. A simplified version of the gradient is proposed. Simulation results across a range of real backplane channels show proper convergence of the gradients and minimal performance loss for the simplified gradient.

This paper provides a framework for analyzing and comparing timing recovery schemes for higher order partial response (PR) channels. Several classes of timing recovery schemes are analyzed. Timing recovery loops employing timing gradients or phase detectors derived from the minimum mean-square error (MMSE) criterion, the maximum likelihood (ML) criterion, and the timing function approach of Mueller and Muller (1976) (MRI) are analyzed and compared. The paper formulates and analyzes MMSE timing recovery in the context of a slope look-up table (SLT), which is amenable for an efficient implementation. The properties and performance of the SLT-based timing loop are compared with the ML and MM loops. Analysis and time step simulations for a practical 16-state PR magnetic recording channel show that the output noise jitter of the ML phase detector is worse than that of the SLT-based phase detector. This is primarily due to the presence of self-noise in the ML detector. Consequently, the SLT-based phase detector is to be preferred. In comparing the SLT and MM based timing loops, it is found that both schemes have similar jitter performance.

This paper presents a rate 16/17 "punctured" time varying maximum transition run (PMTR) block code. It is not possible to achieve a rate 16/17 or higher TMTR block code which completely suppresses the minimum distance error event. However, it is in general, possible to make a tradeoff between obtaining higher code rates and coding gain by puncturing; the space of codewords and limiting the extent to which the minimum distance error event is suppressed. As an example, we obtain a rate 16/17 block code where the minimum distance error event is supported in only 6 out of the 17 possible codeword locations. An implementation of the code is presented and simulation results examining the performance benefits under different conditions are also presented.

The use of complex noise transfer functions for bandpass sigma delta modulation is described and compared with real transfer functions. For bandpass signals centered at higher frequencies, the use of complex noise transfer functions (NTFs) allows performance improvements over a modulator of the same order using real transfer functions. Results are presented that show the performance improvement possible using complex second order modulators.

A multi band approach to oversampled noise shaping analog to digital conversion is described. The multi band A/D converter breaks the signal band into several smaller bands and uses a different band reject noise shaping transfer function for each band. A FIR filter bank attenuates the out-of-band noise for each band and reconstructs the signal. This approach allows performance improvements over conventional noise shaping A/D converters which convert the entire signal band using one noise shaping transfer function. A design example and simulation results where a signal with 512 kHz bandwidth is converted to about 16 bits of resolution is presented.>