While routing failures are rare in contemporary FPGAs, difficulties in routing a design can translate into timing closure failure. However, unlike many customer-visible metrics, such as performance, routability of a design on a given FPGA is challenging to quantify. Nevertheless, FPGA architects and CAD developers monitor several metrics, such as heap operations, wire usage, number of routing iterations, and outstanding congestion during routing iterations, to indirectly assess and compare the routability of different designs on various FPGAs. In academic research these metrics can be correlated against channel width sweeps and experiments varying a small set of connectivity parameters on a fixed architecture. In modern commercial FPGAs routing topology can vary significantly between architectures and detailed connectivity patterns are highly optimized to the physical characteristics of the target process node, making channel width sweeps not applicable to evaluating and optimizing commercial FPGAs. In this work, we introduce a new metric to quantify routability in FPGAs. To this end, we start by extracting routability metrics across a set of experiments on an Agilex device as we reduce its available routing tracks. Next, we introduce our proposed routing struggle metric, derived from heap operations trajectory, to quantify and compare the routability of designs as we progressively maim the routing fabric of the device. Next, we perform several comparisons between Stratix 10 and Agilex FPGAs and show that the Agilex device is significantly more routable, but this routability difference is not captured using traditional routability metrics. However, routing struggle can provide a comparison in terms of routability between the Agilex and Stratix 10 devices that aligns with the trend of maximum operating frequency in progressively shrinking placement regions in our area-constrained experiments. Finally, we show that routing struggle is not limited to Quartus experiments and can also be applied in the academic VTR flow.

This paper describes architectural enhancements in Intel® Agilex™ FPGAs and SoCs. Agilex devices are built on Intel's 10nm process and feature next-generation programmable fabric, tightly coupled with a quad-core ARM processor subsystem, a secure device manager, IO and memory interfaces, and multiple companion transceiver tile choices. The Agilex fabric features multiple logic block enhancements that significantly improve propagation delays and integrate more effectively with the second-generation HyperFlexAgilex™ pipelined routing architecture. Routing connections are re-designed to be point-to-point, dropping intermediate connections featured in prior FPGA generations and replacing them with a wider variety of shorter wire types. Fine-grain programmable clock skew and time-borrowing were introduced throughout the fabric to augment the slack-balancing capabilities of HyperFlex registers. DSP capabilities are also extended to natively support new INT9/BFLOAT16/FP16 formats. Together, along with process and circuit enhancements, these changes support more than 40% performance improvement over the Stratix® 10 family of FPGAs.

This paper describes architectural enhancements in the Altera Stratix? 10 HyperFlex? FPGA architecture, fabricated in the Intel 14nm FinFET process. Stratix 10 includes ubiquitous flip-flops in the routing to enable a high degree of pipelining. In contrast to the earlier architectural exploration of pipelining in pass-transistor based architectures, the direct drive routing fabric in Stratix-style FPGAs enables an extremely low-cost pipeline register. The presence of ubiquitous flip-flops simplifies circuit retiming and improves performance. The availability of predictable retiming affects all stages of the cluster, place and route flow. Ubiquitous flip-flops require a low-cost clock network with sufficient flexibility to enable pipelining of dozens of clock domains. Different cost/performance tradeoffs in a pipelined fabric and use of a 14nm process, lead to other modifications to the routing fabric and the logic element. User modification of the design enables even higher performance, averaging 2.3X faster in a small set of designs.

This paper describes architectural enhancements in the Altera Stratix-V" FPGA architecture, built on a 28nm TSMC process, together with the data supporting those choices. Among the key features are time borrowing flip-flops, a doubling of the number of flip-flops per LUT compared to previous Stratix architectures, a simplified embedded 20kb dual-port RAM block, and error correction that can correct up to 8 adjacent errors. Arithmetic performance is significantly improved using a fast adder with two levels of multi-bit skip. We also describe how the routing architecture and layout is optimized for the 28nm process to take advantage of a wider range of wire thicknesses offered on the different layers, and improvements in performance and routability are obtained without dramatic changes to the repeated floorplan of the logic plus routing fabric.

Metastability is a phenomenon that can cause system failures in digital circuits. It may occur whenever signals are being transmitted across asynchronous or unrelated clock domains. The impact of metastability is increasing as process geometries shrink and supply voltages drop faster than transistor Vts. FPGA technologies are significantly affected since leading edge FPGAs are amongst the first devices to adopt the most recent process nodes. In this paper, we present a comprehensive suite of techniques for modeling, characterizing and optimizing metastability effects in FPGAs. We first discuss a theoretical model of metastability, and verify the predictions using both circuit level simulations and board measurements. Next we show how designers have traditionally dealt with metastability problems and contrast that with the automatic CAD algorithms described in this paper that both analyze and optimize metastability-related issues. Through our detailed experimental results, we show that we can improve the metastability characteristics of a large suite of industrial benchmarks by an average of 268,000 times with our optimization techniques.