Integration of analog and RF circuits with advanced node digital systems has leapfrogged analog circuits by several technology nodes. This has resulted in higher defect rates as well as higher process variations. Another point of pressure is that some application domains, such as the automotive industry, require very low defect rates. To ensure that the circuits are thoroughly tested without increasing the test cost severely, test optimization methods can be applied. Examples of test optimization can include the use of alternate tests, reduced test sets, and built-in self-tests. Defect coverage of the optimized tests needs to be evaluated to ensure high-quality products. For analog circuits, defect definitions are generally continuous and minimum detectable deviation (of hard and soft defects) may differ from one test to another. Finding this detectability point is important to compare potential test conditions. In this paper, we propose an algorithm to determine the minimum detectable defect severity for each defect under given test conditions. Ultimately, this information can be used to find the most sensitive test method that already covers the detection limit of other methods. Experiments on an 8-bit ADC circuit show that the proposed algorithm finds the defect detectability limits of different test methods in only a few search steps and yields accurate results.

The objective of fault simulation is to estimate the fault coverage of a given test input. Established fault models in the analog domain are based on detailed transistor-level netlists. Existing fault simulation tools inject and analyze fault responses at this level of detail. However, extending fault simulation to large circuits, especially when digital signals and/or frequency translation is involved, can be difficult due to the nature of simulations. Designers work with models at higher abstraction levels where simulations are more efficient. The goal of this paper is to bridge the gap between available transistor-level fault simulation tools, where fault simulation can be accurate, and behavioral abstraction levels, where simulation time can be shorter. We aim to achieve this by judiciously adding various functional enhancements to individual functional blocks from a list of templates into their behavioral model until the responses at the two abstraction levels match. Transistor-level simulations are only limited to smaller functional blocks, where they are feasible, and individual fault responses are captured for behavioral simulations. Experimental results on two example circuits, a flash ADC and a PLL, show that accurate simulations can be achieved at a fraction of the simulation time.

Integrated circuit designs are evaluated at various corners defined by choices of the design and process parameters. Considering the large number of corners and the simulation cost of covering all the corners of a large design, it is desirable to identify a subset of the corners that can potentially expose corner case bugs. In an integrated analog coverage management framework, this choice may be influenced by those corners that take one or more component analog IPs close to their individual specification boundaries. Since the admissible state space of an analog IP is multi-dimensional, the same corner may not reach the extreme behaviors for each attribute of the specification, and one needs to identify a subset that covers the extremality. This paper shows that the underlying problem is NP-hard and presents an automated methodology for selecting the corners. A formal analog coverage specification is leveraged by our algorithm, which uses a Satisfiability Modulo Theory (SMT) solver to identify the appropriate corners from the output of multiple Monte Carlo (MC) simulations. The efficacy of the proposed approach is demonstrated over industrial test cases.

Coverage is a key indicator for verification progress, verification closure, and verification sign-off in an integrated circuit design. The notion of coverage management, namely, the use of coverage information across the design hierarchy to identify verification loopholes, is well understood in the digital context, but requires considerable disambiguation in the analog/mixed-signal (AMS) context. This article develops the core artifacts of AMS coverage and presents a comprehensive coverage management approach based on our tool, CoveRT. Our results, gleaned from live industrial designs, demonstrate the benefits of AMS coverage management across the design hierarchy, both in terms of identifying verification gaps, as well as in finding design bugs.

Coverage monitoring is fundamental to design verification. Coverage artifacts are well developed for digital integrated circuits and these aim to cover the discrete state space and logical behaviors of the design. Analog designers are similarly concerned with the operating regions of the design and its response to an infinite and dense input space. Analog variables can influence each other in far more complex ways as compared to digital variables, consequently, the notion of cross coverage, as introduced in the analog context for the first time in this paper, is of high importance in analog design verification. This paper presents the formal syntax and semantics of analog cross coverage artifacts, the methods for evaluating them using our tool kit, and most importantly, the insights that can be gained from such cross coverage analysis.

This paper discusses how adaptive test techniques can be applied to multi-core RF SoCs, together with design implementation and test challenges. Various techniques specific to RF circuits covering calibration trims, power management modules, co-existence issues, concurrent testing, and test measurements are explained. Results on different designs are presented. Together, they highlight the need and scope of adaptive test for RF circuits, and share a new dimension in the test of multi-core circuits, under different constraints of design, test and test equipment.

This paper discusses some specific circuit, and analog DFT techniques and methodologies used in integrated power management (PM) systems to overcome challenges of mixed-signal SoC qualification. They are mainly targeted at achieving the following: 1. Enabling the robust digital and system level test and burn-in (BI) with external supplies by disabling the on-chip PM with robust power-on performance, 2. Minimising external on-board active components in BI board and making the whole BI process more robust, 3. Making the IDDQtests more robust, increasing the IDDQsensitivity by less error prone design methods and enabling IDDQtests possible on analog supplies, and 4. Defining separate BI strategy for the whole PM modules on-chip and enabling it by targeted analog test modes.

Mixed signal SOCs with integrated RF and power management modules have some distinct requirements associated with them. They are often used in portable and battery operated consumer applications, which are extremely cost and power sensitive. This translates into a few unique design and test constraints on the amount of DFT logic integrated, the permissible test time, and power-up of individual modules in the SOC. In this paper, we propose some novel DFT and test techniques which have been devised keeping in mind these constraints, and illustrate how test cost has been significantly reduced in such cost and power constrained mixed signal SOCs. The paper discusses three significant components of the test time and techniques for their reduction through smarter DFT and BIST: (i) RF tests in multiple radio modules, (ii) test and calibration of complex power management logic and voltage regulators, and (iii) improved scan ATPG for all the digital logic. These techniques are being integrated into Texas Instruments' embedded SOCs designed for such portable application, resulting in an overall test cost reduction by half over the previous generation of such SOCs.