In this paper, a new linear-time technique is described for the simulation of lossy lines with frequency-independent R, L, C and G. Exact analytic forms are shown to exist for the frequency-independent lossy line, with application in both the new technique and the conventional convolution method. Numerical convolution formulae that exploit the analytic forms are presented. Experimental results for industrial circuits indicate that the new technique can be 10 and 50 times faster than the convolution and lumped-RLC methods, respectively, for long simulations.>

A general framework for mixed-level circuit and device simulation is described. This framework was used in the development of the simulation program CODECS (coupled device and circuit simulator). Various algorithms to couple the device and circuit simulators for DC and transient analyses have been implemented in CODECS. These algorithms are evaluated based on their convergence properties and run-time performance. This study provides guidelines for choosing a particular coupling algorithm. A modified two-level Newton algorithm is used for DC analysis, whereas a full block-LU decomposition algorithm is used for transient analysis. This combination of algorithms provides reasonable convergence and run-time performance. A simple latency scheme provides a 50% speedup. Coupling for small-signal AC and pole-zero analyses are described.>

Article Free Access Share on Efficient transient simulation of lossy interconnect Authors: Jaijeet S. Roychowdhury Department of Electrical Engineering and Computer Sciences, University of California, Berkeley Department of Electrical Engineering and Computer Sciences, University of California, BerkeleyView Profile , Donald O. Pederson Department of Electrical Engineering and Computer Sciences, University of California, Berkeley Department of Electrical Engineering and Computer Sciences, University of California, BerkeleyView Profile Authors Info & Claims DAC '91: Proceedings of the 28th ACM/IEEE Design Automation ConferenceJune 1991 Pages 740–745https://doi.org/10.1145/127601.127762Published:01 June 1991Publication History 72citation503DownloadsMetricsTotal Citations72Total Downloads503Last 12 Months21Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

A linear time-complexity algorithm for lossy transmission line simulation within arbitrary nonlinear circuits is presented. The method operates by storing information about the state of the line at dynamically selected internal points and using an analytical formulation based on impulse responses to predict the line's future behavior accurately. Previous approaches using impulse responses possess quadratic-time complexity. The proposed method does not require rational or other approximations of transfer functions to achieve linear time-complexity, nor does it increase the size of the simulator's matrix by more than 2 for each transmission line. Experimental results on industrial circuits indicate that, for equivalent or superior accuracy, the state-based method can be faster for simulations of one or more block or data pulses, with speedups of more than 10 and 50 over the convolution and lumped-RLC methods for the longer simulations.>

Mixed-level device and circuit simulation allows the use of one- or two-dimensional numerical models for critical devices in a circuit configuration. CODECS is a mixed-level device and circuit simulator that has been developed to support a variety of numerical models and analyses capabilities. Effective coupling of device and circuit simulation capabilities is achieved by a proper choice of algorithms and architecture. Several examples illustrate the advantages of CODECS for simulating both MOS and bipolar circuits.>

Our original MSPLICE multiprocessor-based circuit simulator showed excellent efficiency with up to 10 processors. As shown in this paper, however, the efficiency of the program drops significantly when over 40 processors are used. A new generation of the MSPLICE program is described which shows high efficiency with up to 99 processors for three different benchmark circuits. Data is compared against predictions made from simulations of an ideal Gauss-Seidel machine model with unit delay, and the data as well as the model are evaluated in light of this comparison. The results from the new implementation are used to study actual limitations that arise as more processors are employed to solve the circuit simulation problem. A major problem identified is that of scheduling overhead and queue contention. Elimination of this bottleneck has led to significant performance improvement. Another bottleneck discovered in the original implementation was that of global data structure contention. Solutions for these and other problems have been implemented in MSPLICE and are currently being used to direct the continued development of the program.