Systematic defects within integrated circuits (ICs) are a significant source of failures in nanoscale technologies. Identification of systematic defects is therefore very important for yield improvement. This paper discusses a diagnosis-driven systematic defect identification methodology that we call layout analysis for systematic IC-defect identification using clustering (LASIC). By clustering images of the layout locations that correspond to diagnosed sites for a statistically large number of IC failures, LASIC uncovers the common layout features. To reduce computation time, only the dominant coefficients of a discrete cosine transform analysis of the layout images are used for clustering. LASIC is applied to an industrial chip and it is found to be effective. In addition, detailed simulations reveal that LASIC is both accurate and effective.

Design for manufacturability (DFM) is essential because of the formidable challenges encountered in nano-scale integrated circuit (IC) fabrication. Unfortunately, it is difficult for designers to understand the cost-benefit tradeoff when tuning their design through DFM to achieve better manufacturability. This paper attempts to assist the designer in meeting this challenge by providing a methodology, called rule assessment of defect-affected regions (RADAR), which uses failing-IC diagnosis results to systematically evaluate the effectiveness of DFM rules. RADAR is applied to the fail data from a 90 nm Nvidia graphics processing unit to demonstrate its viability. Specifically, evaluation of various DFM rules revealed that via-enclosure rules play a more important role than the density-related rules. The yield impact of resolving violations is also quantified. In addition, comprehensive simulation experiments have shown RADAR to be accurate and effective for performing DFM evaluation.

Logic-level simulation has been the de facto method for simulating defect/faulty behavior for various testing tasks since it offers a good tradeoff between accuracy and speed. Unfortunately, by abstracting defect behavior to the logic level (i.e., a fault model), it also discards important information that inevitably results in inaccuracies. This paper describes a fast and accurate defect simulation framework called SLIDER (simulation of layout-injected defects for electrical responses). SLIDER uses well-developed mixed-signal simulation technology that is conventionally used for design verification. There are three innovative aspects that distinguish SLIDER from prior work in this area: 1) accuracy resulting from defect injection taking place at the layout level; 2) speedup resulting from careful and automatic partitioning of the circuit into maximal digital and minimal analog domains for mixed-signal simulation; and 3) complete automation that includes defect generation, defect injection, design partitioning, netlist extraction, mixed-signal simulation, and test-data extraction. The virtual failure data created by SLIDER is useful in a variety of settings that include diagnosis resolution improvement, defect localization, fault model evaluation, and evaluation of yield/test learning techniques that are based on failure data analysis.

Design for manufacturability (DFM) is inevitable because of the formidable challenges encountered in nano-scale integrated circuit (IC) manufacturing. Unfortunately, it is difficult for designers to understand the cost-benefit tradeoff when tuning their design through DFM to achieve better manufacturability. This work attempts to assist the designer in this aspect by providing a methodology (called RADAR --- Rule Assessment of Defect-Affected Regions) which uses failing-IC diagnosis results to systematically evaluate the effectiveness of DFM rules. RADAR is applied to the fail data from a 90nm Nvidia graphics processing unit (GPU) to demonstrate its viability. Specifically, evaluation of the via-enclosure rules revealed that they are much more needed in metal layers 3--6 than the remaining layers.

Systematic defects due to design-process interactions are a significant component of integrated circuit (IC) yield loss in nano-scale technologies. Test structures do not adequately represent the product in terms of feature diversity and feature volume, and therefore are unable to identify all the systematic defects that will affect a product over its manufacturing lifetime. This paper describes a comprehensive methodology that addresses the prevention and identification of systematic defects. For prevention, a method called RADAR (Rule Assessment of Defect-Affected Regions) has been developed for measuring the effectiveness of design-for-manufacturability (DFM) rules in preventing systematic defects that is based on volume diagnosis data. A second method called LASIC (Layout Analysis for Systematic Identification using Clustering), also based on volume diagnosis data, has been developed for identifying systematic defects that escape DFM. To validate RADAR and LASIC, a fast and accurate defect simulation framework called SLIDER (Simulation of Layout-Injected Defects for Electrical Responses) has been developed. SLIDER generates virtual failure data with known defect characteristics. Experiments involving two industrial chips and virtual failure data from SLIDER demonstrate the effectiveness of RADAR and LASIC.

As integrated circuit (IC) manufacturing entered the nano-scale era, defect observability has greatly diminished. As a result, test-fail data diagnosis and mining are playing an indispensable role in providing feedback for yield learning. Accurate simulation of defect behavior is vital to this process but, unfortunately, cannot be achieved with simulation at the logic-level alone. This work proposes a framework to enable fast and accurate defect simulation, by making use of existing and well-developed mixed-signal simulation technology (traditionally used for design verification). While previous work has considered this topic before, the innovation here centers on two aspects: (i) accuracy resulting from defect injection taking place at the layout level, (ii) speedup resulting from careful and automatic partitioning of the circuit into digital and analog domains for mixed-signal simulation, and (iii) complete automation that involves defect injection, design partitioning, netlist extraction, mixed-signal simulation, and test-data extraction. The mixed-signal framework developed can be applied in a variety of settings that include diagnosis resolution improvement, defect localization, fault model evaluation, and virtual failure data creation. Experiments demonstrate that the proposed framework is scalable to handle large designs efficiently. A second set of experiments demonstrates how defect localization can be dramatically improved (>; 53%) by more accurate defect simulation.

A technique is proposed to automatically predict whether a failing chip has a bridge defect. Logic diagnosis is performed using scan test results to identify candidate nets. Several relevant features of the test data are measured for net pairs that consist of the diagnosis candidates and other nets in close physical proximity. Based on these features, rules are constructed to identify defects that fully exhibit classic bridge behaviors, while the remaining chips are classified using a forest of decision trees. Results indicate that a population of chips failing due to bridges can indeed be extracted with very high accuracy. Finally, the method correctly classifies 41 commercially-fabricated chips that underwent PFA.

Systematic defects due to design-process interactions are a dominant component of integrated circuit (IC) yield loss in nano-scaled technologies. Test structures do not adequately represent the product in terms of feature diversity and feature volume, and therefore are unable to identify all the systematic defects that affect the product. This paper describes a method that uses diagnosis to identify layout features that do not yield as expected. Specifically, clustering techniques are applied to layout snippets of diagnosis-implicated regions from (ideally) a statistically-significant number of IC failures for identifying feature commonalties. Experiments involving an industrial chip demonstrate the identification of possible systematic yield loss due to lithographic hotspots.

Sub-wavelength lithography uses light waves that have a longer wavelength than the feature size that is being printed. Image distortions are an inevitable consequence of this situation, even after resolution enhancement techniques have been applied. This paper studies in detail how the image distortion in a fabricated IC can impact test and critical-area yield loss. Particularly, lithography simulation is performed on the desired pattern to predict the printed (distorted) pattern. The impact on critical-area yield loss is studied using both the desired pattern and the printed pattern. Similarly, the impact on test is studied using inductive fault analysis on both the desired pattern and the printed pattern. Even under the assumption of the best process conditions, experiment results indicate that the difference in misdirected test effort can be as large as 8.0% and the difference in the critical-area yield calculations is about 3.4% for a large design. The more accurate analysis requires a runtime increase of 5X on average.

Integrated circuit (IC) diagnosis typically analyzes failed chips by reasoning about their responses to test patterns to deduce what has gone wrong. Current trends use diagnosis as the first step in extracting valuable information from a large population of failing ICs that include, for example, design-feature failure rates and defect-occurrence statistics. However, it is difficult to examine the accuracy of these techniques because of the unavailability of sufficient fail data where such information is known. This paper describes an approach for benchmarking and verifying diagnosis techniques through failure population creation that builds on prior work in this area. Specifically, we describe how a population of realistic IC failures is created through circuit-level simulation of extracted layouts. The most novel feature of the work is that the virtual test responses produced are both a precise function of defect type and the three-dimensional location within the layout. The extended approach is demonstrated using twelve placed-and-routed circuits. An example application of the developed framework is given to illustrate the utility of having a failure population where the location and type of defect are known a priori.

We propose to achieve and maintain ultra-high quality of digital circuits on a per-design basis by (i) monitoring the type of failures that occur through volume diagnosis, and (ii) changing the test patterns to match the current failure population characteristics. Opposed to the current approach that assumes sufficient quality levels are maintained using the tests developed during the time of design, the methodology described here presupposes that fallout characteristics can change over time but with a time constant that is sufficiently slow, thereby allowing test content to be altered so as to maximize coverage of the failure types actually occurring. Even if this assumption proves to be false, the test content can be tuned to match the characteristics of the fallout population if the fallout characteristics are unchanging. Under either scenario, it should be then possible to minimize DPPM for a given constraint on test costs, or alternatively ensure that DPPM does not exceed some pre-determined threshold. Our approach does not have to cope with situations where fallout characteristics change rapidly (e.g. excursion), since there are existing methods to deal with them. Our methodology uses a diagnosis technique that can extract defect activation conditions, a new model for estimating DPPM, and an efficient test selection method for reducing DPPM based on volume diagnosis results. Circuit-level simulation involving various types of defects shows that DPPM could be reduced by 30% using our methodology. In addition, experiments on a real silicon chip failures show that DPPM can be significantly reduced, without additional test execution cost, by altering the content (but not the size) of the applied test set.

Traditional software-based diagnosis of failing chips typically identifies several lines where the failure is believed to reside. However, these lines can span across multiple layers and can be very long in length. This makes physical failure analysis difficult. In contrast, there are emerging diagnosis techniques that identify both the faulty lines as well as the neighboring conditions for which an affected line becomes faulty. In this paper, an approach is presented to improve failure localization by automatically analyzing the information associated with the outcome of diagnosis. Experimental results show a significant improvement in failure localization when this method is applied to 106 real IC failures.