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David Wang 0003

dblp:72/1614-3 · DBLP profile ↗
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5ranked-venue papers
0as first author
2since 2021 · last 2021
—ORCID · conflict

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 2 since 2021Artificial intelligence and machine learning · 1Software engineering, systems software and programming languages · 1 · 1 since 2021Databases, data management, data science and information retrieval · 1Graphics, computer vision, multimedia, augmented reality and games · 1Applied, interdisciplinary, general and emerging computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Memory systems · 55% Hardware accelerators and domain-specific architectures · 44% Performance modeling and evaluation · 1%
Databases, data mining, and information retrieval
2 papers
Data integration and cleaning · 56% Knowledge graphs · 44%
Interdisciplinary, comprehensive, and emerging computing
2 papers
Environmental and earth informatics · 100%

Topics — the 8 heaviest of 11, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems › processing-in-memory
DRAM-PIM
0.512021
Hardware Architecture and Software Stack for PIM Based on Commercial DRAM Technology : Industrial Product · ISCA 2021
Hardware accelerators and domain-specific architectures
machine learning accelerator
0.512021
Hardware Architecture and Software Stack for PIM Based on Commercial DRAM Technology : Industrial Product · ISCA 2021
Hardware accelerators and domain-specific architectures › machine learning accelerator
neural network accelerator
0.512021
Hardware Architecture and Software Stack for PIM Based on Commercial DRAM Technology : Industrial Product · ISCA 2021
Memory systems
processing-in-memory
0.512021
Hardware Architecture and Software Stack for PIM Based on Commercial DRAM Technology : Industrial Product · ISCA 2021
Memory systems
DRAM
0.222021
Hardware Architecture and Software Stack for PIM Based on Commercial DRAM Technology : Industrial Product · ISCA 2021
Fully-Buffered DIMM Memory Architectures: Understanding Mechanisms, Overheads and Scaling · HPCA 2007
Memory systems
memory controller
0.012007
Fully-Buffered DIMM Memory Architectures: Understanding Mechanisms, Overheads and Scaling · HPCA 2007
Performance modeling and evaluation
scheduling policy
0.012007
Fully-Buffered DIMM Memory Architectures: Understanding Mechanisms, Overheads and Scaling · HPCA 2007
Data integration and cleaning › semantic integration
ontology-based data integration
0.012006
Integrating ecoinformatics resources on the semantic web · WWW 2006

Methods — techniques the papers use, named apart from their topics

software stack development · 0.52.5d/3d stacking · 0.5triple shop · 0.1semantic web · 0.1ontology · 0.1SPARQL · 0.1OWL · 0.1simulation · 0.1
YearPublicationVenuePosition
2021 Aquabolt-XL: Samsung HBM2-PIM with in-memory processing for ML accelerators and beyond
abstract
Using PIM to overcome memory bottleneck • Although various bandwidth increase methods have been proposed, it is physically impossible to achieve a breakthrough increase. - Limited by # of PCB wires, # of CPU ball, and thermal constraints • PIM has been proposed to improve performance of bandwidth-intensive workloads and improve energy efficiency by reducing computing-memory data movement.
Jin Hyun Kim, Shinhaeng Kang, Sukhan Lee 0002, Woongjae Song, Yuhwan Ro, Seungwon Lee 0006, David Wang 0003, Hyunsung Shin, BengSeng Phuah, Jihyun Choi, Jinin So, Yeongon Cho, Joon-Ho Song, Jangseok Choi, Jeonghyeon Cho, Kyomin Sohn, Young-Soo Sohn, Kwang-Il Park, Nam Sung Kim
HCS8
2021 Hardware Architecture and Software Stack for PIM Based on Commercial DRAM Technology : Industrial Product
abstract
Emerging applications such as deep neural network demand high off-chip memory bandwidth. However, under stringent physical constraints of chip packages and system boards, it becomes very expensive to further increase the bandwidth of off-chip memory. Besides, transferring data across the memory hierarchy constitutes a large fraction of total energy consumption of systems, and the fraction has steadily increased with the stagnant technology scaling and poor data reuse characteristics of such emerging applications. To cost-effectively increase the bandwidth and energy efficiency, researchers began to reconsider the past processing-in-memory (PIM) architectures and advance them further, especially exploiting recent integration technologies such as 2.5D/3D stacking. Albeit the recent advances, no major memory manufacturer has developed even a proof-of-concept silicon yet, not to mention a product. This is because the past PIM architectures often require changes in host processors and/or application code which memory manufacturers cannot easily govern. In this paper, elegantly tackling the aforementioned challenges, we propose an innovative yet practical PIM architecture. To demonstrate its practicality and effectiveness at the system level, we implement it with a 20nm DRAM technology, integrate it with an unmodified commercial processor, develop the necessary software stack, and run existing applications without changing their source code. Our evaluation at the system level shows that our PIM improves the performance of memory-bound neural network kernels and applications by 11.2× and 3.5×, respectively. Atop the performance improvement, PIM also reduces the energy per bit transfer by 3.5×, and the overall energy efficiency of the system running the applications by 3.2×.
Sukhan Lee 0002, Shinhaeng Kang, Jaehoon Lee 0005, Eojin Lee, Seungwoo Seo, Hosang Yoon, Seungwon Lee 0006, Kyounghwan Lim, Hyunsung Shin, Jinhyun Kim, Seongil O, Anand Iyer, David Wang 0003, Kyomin Sohn, Nam Sung Kim
ISCA14
2007 Fully-Buffered DIMM Memory Architectures: Understanding Mechanisms, Overheads and Scaling
abstract
Performance gains in memory have traditionally been obtained by increasing memory bus widths and speeds. The diminishing returns of such techniques have led to the proposal of an alternate architecture, the fully-buffered DIMM. This new standard replaces the conventional memory bus with a narrow, high-speed interface between the memory controller and the DIMMs. This paper examines how traditional DDRx based memory controller policies for scheduling and row buffer management perform on a fully-buffered DIMM memory architecture. The split-bus architecture used by FBDIMM systems results in an average improvement of 7% in latency and 10% in bandwidth at higher utilizations. On the other hand, at lower utilizations, the increased cost of serialization resulted in a degradation in latency and bandwidth of 25% and 10% respectively. The split-bus architecture also makes the system performance sensitive to the ratio of read and write traffic in the workload. In larger configurations, we found that the FBDIMM system performance was more sensitive to usage of the FBDIMM links than to DRAM bank availability. In general, FBDIMM performance is similar to that of DDRx systems, and provides better performance characteristics at higher utilization, making it a relatively inexpensive mechanism for scaling capacity at higher bandwidth requirements. The mechanism is also largely insensitive to scheduling policies, provided certain ground rules are obeyed
Brinda Ganesh, Aamer Jaleel, David Wang 0003, Bruce L. Jacob
HPCA3
2006 Using the Semantic Web to Integrate Ecoinformatics Resources
Cynthia Sims Parr, Andriy Parafiynyk, Joel Sachs, Lushan Han, Li Ding 0001, Tim Finin, David Wang 0003
AAAI8
2006 Integrating ecoinformatics resources on the semantic web
abstract
We describe ELVIS (the Ecosystem Location Visualization and Information System), a suite of tools for constructing food webs for a given location. We express both ELVIS input and output data in OWL, thereby enabling its integration with other semantic web resources. In particular, we describe using a Triple Shop application to answer SPARQL queries from a collection of semantic web documents. This is an end-to-end case study of the semantic web's utility for ecological and environmental research.
Cynthia Sims Parr, Andriy Parafiynyk, Joel Sachs, Li Ding 0001, Sandor Dornbush, Tim Finin, David Wang 0003, Allan Hollander
WWW7