Boiling Liquid Expanding Vapour Explosion (BLEVE) is a high-energy event characterised by intense blast waves that pose serious safety risks. Accurate prediction of the resulting overpressure wave is essential for knowledge-intensive engineering analysis and decision support. While empirical methods are available for predicting overpressure in simple BLEVE scenarios, they fail to capture nonlinear relationships in multi-feature and complex conditions. Computational Fluid Dynamics (CFD) methods offer high accuracy in overpressure wave prediction but are computationally intensive, expensive to use and difficult to integrate into automated or real-time engineering workflows. Machine learning models offer a promising alternative for rapid predictions, but their limited interpretability, particularly in deep learning architectures, poses a significant barrier to integration into real-world engineering systems. This study proposes a systematic approach combining machine learning, explainable artificial intelligence, and symbolic regression for BLEVE overpressure prediction. A feedforward neural network model is developed and interpreted using SHapley Additive exPlanations (SHAP). Global SHAP analysis identified nine features with the most significant contributions, which were subsequently used to train a global surrogate model via symbolic regression. This approach yielded an explicit mathematical expression that approximates the behaviour of the original neural network. The derived equation achieved a relative error of 15.73% on simulated data and 35.45% on experimental data, outperforming existing empirical formulas. This research demonstrates the potential of combining black-box machine learning models with xAI techniques to develop interpretable and reliable equations for blast load prediction. More importantly, it introduces a novel data-driven methodology of data-model-interpretation-equation that formalises engineering knowledge by transforming black-box models into explicit and interpretable computational representations.

The vast majority of text-independent speaker recognition systems rely on intermediate-sized vectors (i-vectors), which are compared by probabilistic linear discriminant analysis (PLDA). This paper proposes a PLDA-alike approach with restricted Boltzmann machines for i-vector based speaker recognition: two deep architectures are presented and examined, which aim at suppressing channel effects and recovering speaker-discriminative information on back-ends trained on a small dataset. Experiments are carried out on the MOBIO SRE'13 database, which is a challenging and publicly available dataset for mobile speaker recognition with limited amounts of training data. The experiments show that the proposed system outperforms the baseline i-vector/PLDA approach by relative gains of 31% on female and 9% on male speakers in terms of half total error rate.

When we analyze the scaling factors of the recent technology nodes, we come to the conclusion that the geometrical scaling scenario has been replaced by the electrical scaling and hence the electrical characterization of these really challenging technologies becomes an absolute must. However, the extremely small process windows, and the 3-dimensional nature of the FinFET devices and the complicated interconnect schemes, make this characterization very difficult. Systematic failure modes and their dependence on the layout patterns are extremely complex and almost impossible to detect in-line. Moreover, soft failures become much more prevalent due to process marginalities and present not only yield but also reliability hazards. Hence, the new fault models must be created that take into account layout patterns and layout-process interactions to allow for more efficient testing and reliability risk screening. This talk will present novel approaches to electrical characterization of the dominant failure modes, its impact on the test generation and execution, and the need for tracking this information all the way from the front end process to the test and assembly stages of IC manufacturing.

This paper presents a simple but elegant approach to effectively automate the time-consuming silicon debug procedure for microprocessor embedded memory arrays that allow no direct test modes, based on sequential ATPG with built-in design-for-debug methodology.

This paper describes the SuperSPARC II clock controller. This controller allows the internal clock to be disabled during the chip's normal operation. Then any number of internal clock pulses can be issued in a controlled fashion. The clock can return to the free running mode after being disabled. All clock control is done in a way that produces no glitches on the internal clock signal The clock controller can be accessed through the IEEE 1149.1 interface, making it useful at the chip level and at the module or system level.

This paper describes a structured design-for-debug methodology that provides observability throughout an entire chip. It makes use of existing design-for-testability (DFT) features on the chip and is part of the overall DFT strategy. The implementation of the methodology on the SuperSPARC II microprocessor is described. This methodology has been instrumental in the successful silicon debug and timely shipment of the chip.

In this paper we propose a very-low-voltage (VLV) testing technique for CMOS logic ICs. Voltage dependence of CMOS logic circuit operation in the presence of resistive shorts and hot carrier damage is studied. It is shown that at certain much-lower-than-normal power supply voltage, weak CMOS logic ICs due to the presence of these flaws can be forced to malfunction while truly good ICs continue to function. Very-low-voltage testing also detects pattern dependent faults caused by resistive shorts. Because of its simplicity and because there is no overhead associated with it, very-low-voltage testing can easily be applied to chips and circuit boards as a production test, field test, or failure diagnosis technique.>

The resistance dependence, voltage dependence, temperature dependence, and pattern dependence properties of CMOS logic gate operation in the presence of gate oxide shorts are analyzed. The analysis is based on realistic defect models that incorporate the resistive nature of gate oxide shorts and the difference between gate oxide shorts in n- and p-channel transistors.>

This paper studies the effects of shorts within CMOS gates. Dynamic as well as static gate properties are analyzed as a function of the short’s resistance. Increased propagation delay is found to be a common dynamic effect. Circuit behavior can change drastically with small variations in a short’s resistance. It is found that faults caused by transistor gate-to-source and gate-to-drain shorts can be dependent not only on inputs of gates containing the faults but also on other signals. This pattern dependence due to “resistive shorts” can invalidate tests generated using normal TPG procedures.

This letter discusses the equivalence between the pre- and post-permutation algorithms for the fast Hartley transform (FHT). Some improvements are made to two recently published FHT programs.

A three-dimensional (3-D) Discrete Fourier Transform (DFT) algorithm for real data using the one-dimensional Fast Hartley Transform (FHT) is introduced. It requires the same number of one-dimensional transforms as a direct FFT approach but is simpler and retains the speed advantage that is characteristic of the Hartley approach. The method utilizes a decomposition of the cas function kernel of the Hartley transform to obtain a temporary transform, which is then corrected by some additions to yield the 3-D DFT. A Fortran subroutine is available on request.

The fast Hartley transform algorithm introduced in 1984 offers an alternative to the fast Fourier transform, with the advantages of not requiring complex arithmetic or a sign change of i to distinguish inverse transformation from direct. A two-dimensional extension is described that speeds up Fourier transformation of real digital images.