EDBT 2026 Demo / reviewers in the wild / expert
Simon Polstra
dblp:72/1762
· DBLP profile ↗
4ranked-venue papers
0as first author
0since 2021 · last 2018
0009-0006-2653-5312ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3Applied, interdisciplinary, general and emerging computing · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Electronic design automation · 48% Embedded and real-time systems · 39% Performance modeling and evaluation · 13% |
Topics — the 7 heaviest of 8, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
design space exploration |
0.1 | 2 | 2008 | Daedalus: toward composable multimedia MP-SoC design · DAC 2008 A Systematic Approach to Exploring Embedded System Architectures at Multiple Abstraction Levels · IEEE Trans. Computers 2006 |
Embedded and real-time systems › embedded hardware platform
MPSoC |
0.1 | 1 | 2008 | Daedalus: toward composable multimedia MP-SoC design · DAC 2008 |
Electronic design automation
system-level design |
0.1 | 1 | 2008 | Daedalus: toward composable multimedia MP-SoC design · DAC 2008 |
Embedded and real-time systems
embedded system design |
0.1 | 1 | 2006 | A Systematic Approach to Exploring Embedded System Architectures at Multiple Abstraction Levels · IEEE Trans. Computers 2006 |
Performance modeling and evaluation
system-level analysis |
0.1 | 1 | 2006 | A Systematic Approach to Exploring Embedded System Architectures at Multiple Abstraction Levels · IEEE Trans. Computers 2006 |
Embedded and real-time systems › real-time embedded systems
multimedia embedded systems |
0.0 | 1 | 2008 | Daedalus: toward composable multimedia MP-SoC design · DAC 2008 |
Embedded and real-time systems › embedded hardware platform
heterogeneous embedded platform |
0.0 | 1 | 2006 | A Systematic Approach to Exploring Embedded System Architectures at Multiple Abstraction Levels · IEEE Trans. Computers 2006 |
Methods — techniques the papers use, named apart from their topics
system-level synthesis · 0.1application mapping · 0.1system-level simulation · 0.1multi-objective optimization · 0.1analytical modeling · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2018 | Communication-centric analysis of complex embedded computing systems: work-in-progressabstractWe show experimental evidence and argue that communication-centric modelling of complex embedded computing systems provides predictive power over the workload dependent behaviour of these systems. System and external observables included in this behaviour can be utilised in the system's analysis. We provide the preliminary results from our detection (monitoring) and imitation (simulation) phases, both part of a larger workflow in development. Uraz Odyurt, Hugo Meyer, Simon Polstra, Evangelos Paradas, Ignacio Gonzalez Alonso, Andy D. Pimentel |
EMSOFT | 3 |
| 2009 | An implementation of the SANE Virtual Processor using POSIX threads
Michiel W. van Tol, Chris R. Jesshope, Mike Lankamp, Simon Polstra |
J. Syst. Archit. | 4 |
| 2008 | Daedalus: toward composable multimedia MP-SoC designabstractDaedalus is a system-level design flow for the design of multiprocessor system-on-chip (MP-SoC) based embedded multimedia systems. It offers a fully integrated tool-flow in which design space exploration (DSE), system-level synthesis, application mapping, and system prototyping of MP-SoCs are highly automated. In this paper, we describe our first industrial deployment experiences with the Daedalus framework. Daedalus is currently being deployed in the early stages of the design of an image compression system for very high resolution cameras targeting medical appliances. In this context, we performed a DSE study with a JPEG encoder application, which exploits both task and data parallelism. This application was mapped onto a range of different MP-SoC architectures. We achieved a performance speed-up of up to 20x compared to a single processor system. In addition, the results show that the Daedalus high-level MP-SoC models accurately predict the overall system performance, i.e., the performance error is around 5%. Hristo Nikolov, Mark Thompson 0001, Todor P. Stefanov, Andy D. Pimentel, Simon Polstra, Raj Bose, Claudiu Zissulescu, Ed F. Deprettere |
DAC | 5 |
| 2006 | A Systematic Approach to Exploring Embedded System Architectures at Multiple Abstraction LevelsabstractThe sheer complexity of today's embedded systems forces designers to start with modeling and simulating system components and their interactions in the very early design stages. It is therefore imperative to have good tools for exploring a wide range of design choices, especially during the early design stages, where the design space is at its largest. This paper presents an overview of the Sesame framework, which provides high-level modeling and simulation methods and tools for system-level performance evaluation and exploration of heterogeneous embedded systems. More specifically, we describe Sesame's modeling methodology and trajectory. It takes a designer systematically along the path from selecting candidate architectures, using analytical modeling and multiobjective optimization, to simulating these candidate architectures with our system-level simulation environment. This simulation environment subsequently allows for architectural exploration at different levels of abstraction while maintaining high-level and architecture-independent application specifications. We illustrate all these aspects using a case study in which we traverse Sesame's exploration trajectory for a motion-JPEG encoder application. Andy D. Pimentel, Cagkan Erbas, Simon Polstra |
IEEE Trans. Computers | 3 |