This paper presents a verification methodology for configurable processor cores. The simulation-based approach uses directed diagnostics and pseudo-random program generators both of which are tailored to specific processor instances. A configurable and extensible test-bench serves as the framework for the verification process and offers components necessary for the complete SOC verification. Coverage analysis provides an evaluation of how well a specific design has been exercised, of the breadth of the configuration space explored, and suggests improvements to the process. The results of the analysis show that our methodology achieves good verification coverage of the processor implementation.

This paper describes the third generation configurable and extensible Xtensa/sup TM/ processor with enhanced DSP functionality targeted to System-On-Chip (SOC) designs. Xtensa III processor family can be configured with an IEEE-compatible floating point unit (FPU) and/or a powerful, energy efficient Vector Integer coprocessor, both implemented using Tensilica Instruction Extension (TIE) language and automatically integrated with the Xtensa base processor core.