The artwork of integrated circuit designs is usually available in the form of hierarchical specification, in which each cell is made up of geometric primitives and references to other cells. Such a representation captures structure and repetition in the layout. As the realizable device count of integrated circuits increases with every passing year there is an increasing trend towards structured design approaches that result in even greater degrees of regularity and hierarchy. Yet the typical approach to design verification requires fully instantiating the hierarchical representation thereby removing all structure from it. Consequently much time is spent repeating the analyses of identical cells. This paper presents a general approach to exploiting hierarchy and repetition in the analysis of integrated circuit designs, and includes details of a circuit extraction algorithm that uses this approach. The implementation and performance of such a system is also described.