Demo Data from EDBT 2026 / reviewers in the wild / expert
Shigeo Kaneda
dblp:72/2250
· DBLP profile ↗
13ranked-venue papers
4as first author
0since 2021 · last 2018
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Artificial intelligence and machine learning · 6 · 2 first-authorSoftware engineering, systems software and programming languages · 4Applied, interdisciplinary, general and emerging computing · 4Systems, architecture and hardware · 2 · 2 first-authorGraphics, computer vision, multimedia, augmented reality and games · 2 · 1 first-authorHuman-computer interaction and ubiquitous computing · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Artificial intelligence
1 paper |
Kernel, tree and ensemble methods · 50% Knowledge representation and reasoning · 50% | |
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Hardware reliability and fault tolerance · 87% Memory systems · 13% | |
| Theoretical computer science
2 papers |
Coding theory · 100% |
Topics — the 6 heaviest of 7, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Machine learning › Kernel, tree and ensemble methods
decision tree learning |
0.0 | 1 | 1995 | On Handling Tree-Structured Attributed in Decision Tree Learning · ICML 1995 |
Hardware reliability and fault tolerance › error correction
error-correcting codes |
0.0 | 2 | 1984 | A Class of Odd-Weight-Column SEC-DED-SbED Codes for Memory System Applications · IEEE Trans. Computers 1984 Single Byte Error Correcting - Double Byte Error Detecting Codes for Memory Systems · IEEE Trans. Computers 1982 |
Hardware reliability and fault tolerance
memory reliability |
0.0 | 2 | 1984 | A Class of Odd-Weight-Column SEC-DED-SbED Codes for Memory System Applications · IEEE Trans. Computers 1984 Single Byte Error Correcting - Double Byte Error Detecting Codes for Memory Systems · IEEE Trans. Computers 1982 |
Coding theory › error-correcting codes
error detection and correction |
0.0 | 2 | 1984 | A Class of Odd-Weight-Column SEC-DED-SbED Codes for Memory System Applications · IEEE Trans. Computers 1984 Single Byte Error Correcting - Double Byte Error Detecting Codes for Memory Systems · IEEE Trans. Computers 1982 |
Coding theory › error-correcting codes › burst error correction
byte error control codes |
0.0 | 1 | 1982 | Single Byte Error Correcting - Double Byte Error Detecting Codes for Memory Systems · IEEE Trans. Computers 1982 |
Memory systems › memory architecture
byte-organized memory |
0.0 | 2 | 1984 | A Class of Odd-Weight-Column SEC-DED-SbED Codes for Memory System Applications · IEEE Trans. Computers 1984 Single Byte Error Correcting - Double Byte Error Detecting Codes for Memory Systems · IEEE Trans. Computers 1982 |
Methods — techniques the papers use, named apart from their topics
odd-weight-column code construction · 0.0SbEC-DbED code construction · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2018 | Community Energy Management System To Encourage Power Saving CompetitionabstractIn Japan, solid oxide fuel cells (SOFCs) are proliferating as highly efficient domestic fuel cells. To fully utilize SOFCs, we proposed a small CEMS (community energy management system) in a conventional study. However, in that study, electricity generation was evenly allocated into each of three houses with no competition among the homes. In addition, the graphic user interface (GUI) lacked an element to reduce energy consumption. We therefore propose a small-scale CEMS that includes a mechanism for competition among the homes and through which a home can profit from low energy consumption. Specifically, this paper theoretically clarifies that the power generation of each home's SOFC should be equal to the average of all the other homes. This amount is mathematically bounded. We designed an experimental prototype of the proposed CEMS using goal-oriented analysis with the goal of encouraging users to save electricity. We implemented and evaluated the small-scale CEMS system based on this design policy in three real homes over a two-month period. Our experimental evaluation clarified the cost-reduction effect of the proposed CEMS and the GUI's ability to engender a competitive consciousness for energy saving among the homes. Takahiro Fujiwara, Toshihiko Tanaka, Kai Takashima, Shigeo Kaneda |
COMPSAC (2) | 4 |
| 2018 | Development of Bicycle Simulator with Tilt Angle Control Tilt AngleabstractBicycles are a healthy and eco-friendly form of travel. Information about dangerous points (hazards) on roads is important for bicycle-riding safety. We proposed a method to detect road hazards using sensors attached to a bicycle in a prior conventional study. The conventional approach needs training data for machine learning, requiring the bicycle to travel over hazardous areas repeatedly. Not only is this is dangerous, it is also difficult to collect sufficiently large amounts of data. A bicycle simulator is a potential solution to this problem. Commercial bicycle simulators have been developed in Japan. However, the bicycle body is fixed, thus making the ride feel unnatural. This type of bicycle simulator is not suitable for gathering hazard data. We therefore propose a bicycle simulator capable of tilt angle control that runs in a three-dimensional (3D) virtual space. The built-in sensors send the speed and front-wheel angle information to the control unit. A new tilt angle is then calculated by the control unit and the information is sent to an AC servomotor to achieve this new tilt angle. Simultaneously, a 3D view of a virtual course is generated using the calculated results. By using our previously proposed rotation center tracking method, left and right steering actions can be observed by the system. This system allows for dangerous situations to be easily and repeatedly created with no danger to the rider. Tetsuji Yamaguchi, Akira Yamada 0007, Takeshi Fujiwara, Ryoichi Takahashi, Tetsuya Shimada, Yuki Ishida, Koichiro Ueda, Shigeo Kaneda |
COMPSAC (2) | 8 |
| 2017 | Visualization Method for Bicycle Rider Behavior Analysis Using a SmartphoneabstractWe previously proposed a bicycle rider behavior visualization method using a probe bicycle equipped with an accurate speed sensor, a rotary encoder to measure handle angle, and a sensor to detect tilt of the bicycle body. However, the probe bicycle is expensive and inhibits wide use of this visualization method. To resolve this problem, we employ a smartphone as the sensor device. This newly proposed method focuses on the azimuth angle because the magnetic sensor is robust to the unwanted effects of bicycle body vibration. A prototype system has been implemented with an Android smartphone-the Sony Corp.'s Xperia. The visualization results generated by the proposed approach are comparable to those of the conventional probe bicycle approach. Using the prototype system, we evaluated the difference between young and aged riders. This experiment statistically clarified a decline in bicycle control for aged riders. Hajime Kato, Yuto Sakajyo, Shigeo Kaneda |
COMPSAC (2) | 3 |
| 2017 | Visualization Method Using Probe Bicycle to Analyze Bicycle Rider's Control BehaviorabstractA bicycle is a useful vehicle in our daily lives, and requires characteristic techniques such as steering control at a constant speed. Since bicycles are commonly used like cars, analyzing their operating condition is essential. Nevertheless, there is little previous research that has succeeded in designing a low-cost method to analyze the operating condition. In the current study, we present a more reasonable model of the visualization of bicycle control behavior using two-dimensional (2-D) plots. In the model, four steps are taken: (1) acquire sensor information from the bicycle, (2) calculate the movement trajectory of the front and rear wheels using the bicycle equations, (3) derive the rotation center, and (4) extract the 2-D plots. As a result, it was possible to visually anticipate (1) a rider's control from the curvature center and trajectory of the front-wheel and (2) the actual behavior and its quality from the rear-wheel. Since it requires accurate speed, steering angle, and body tilt angle to calculate the movement trajectory, we designed a special probe bicycle that could directly obtain these parameters. By using this probe bicycle, four points were clarified. (1) At turning, the bicycle rider sets a target turning center, which is the center of turning. (2) An I-shaped rotation center trajectory appears when the bicycle is going straight, and a V-shaped rotation center locus appears when turning. (3) The distribution trend of the curvature center differs greatly between the front and rear wheels. (4) The quality of turn can be evaluated by the distribution trend. The 2-D plots enabled us to observe the quality of the rider's control like an X-ray. Ryoichi Takahashi, Kazuki Miki, Shigeo Kaneda |
COMPSAC (2) | 3 |
| 2006 | Automatic Updating of a Book Storage Database in a Ubiquitous Library Information System
Hideaki Araki, Hirohide Haga, Shigeo Kaneda |
UIC | 3 |
| 1998 | Turning majority voting classifiers into a single decision treeabstractThis paper addresses the issues of intelligibility, classification speed, and required space in majority voting classifiers. Methods that classify unknown cases using multiple classifiers (e.g. bagging, boosting) have been actively studied in recent years. Since these methods classify a case by taking majority voting over the classifiers, the reasons behind the decision cannot be described in a logical form. Moreover, a large number of classifiers is needed to significantly improve the accuracy. This greatly increases the amount of time and space needed in classification. To solve these problems, a method for learning a single decision tree that approximates the majority voting classifiers is proposed in this paper. The proposed method generates if-then rules from each classifier, and then learns a single decision tree from these rules. Experimental results show that the decision trees by our method are considerably compact and have similar accuracy compared to bagging. Moreover, the proposed method is 8 to 24 times faster than bagging in classification. Yasuhiro Akiba, Shigeo Kaneda, Hussein Almuallim |
ICTAI | 2 |
| 1996 | A Knowledge Revision Learner Using Artificially Generated Examples
Megumi Ishii, Hussein Almuallim, Shigeo Kaneda |
IEA/AIE | 3 |
| 1996 | KOA: General Affairs Expert System with Easy Customization
Shigeo Kaneda, Katsuyuki Nakano, Daizi Nanba, Hisazumi Tsuchida, Megumi Ishii, Fumio Hattori |
IEA/AIE | 1 |
| 1996 | INTERFACER: A user interface tool for interactive expert-systems
Shigeo Kaneda, Megumi Ishii, Fumio Hattori, Tsukasa Kawaoka |
Decis. Support Syst. | 1 |
| 1995 | On Handling Tree-Structured Attributed in Decision Tree Learning
Hussein Almuallim, Yasuhiro Akiba, Shigeo Kaneda |
ICML | 3 |
| 1994 | Two Methods for Learning ALT-J/E Translation Rules from Examples and a Semantic Hierarchy
Hussein Almuallim, Yasuhiro Akiba, Takefumi Yamazaki, Akio Yokoo, Shigeo Kaneda |
COLING | 5 |
| 1984 | A Class of Odd-Weight-Column SEC-DED-SbED Codes for Memory System ApplicationsabstractError correcting codes are widely used in memory systems to increase reliability. Especially in a memory systern that uses byte-organized memory chips, which each contain b (≫1) output bits, a single chip failure is likely to affect many bits within a byte. Single-bit error correcting-double bit error detecting-single b-bit byte error detecting codes (SEC-DED-SbED codes) are suitable for increasing the reliability of memory system. This correspondence presents a new class of odd-weight-column SEC-DED-SbED codes for b = 4. The code length is 2r-1- 2[r/2], where r is the number of check bits and [ ] denotes the ceiling or next largest integer. The proposed SEC-DED-S4ED codes are the best-known codes. Shigeo Kaneda |
IEEE Trans. Computers | 1 |
| 1982 | Single Byte Error Correcting - Double Byte Error Detecting Codes for Memory SystemsabstractIn a memory that uses byte-organized memory chips, each containing b (≥2) output bits, a single chip failure is likely to affect many bits within a byte. Single byte error correcting–double byte error detecting codes (SbEC–DbED codes) are used in this kind of memory system to increase reliability. Shigeo Kaneda, Eiji Fujiwara |
IEEE Trans. Computers | 1 |