Demo Data from EDBT 2026 / reviewers in the wild / expert
Katsuaki Takagi
dblp:72/2502
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 1980
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Integrated circuit design · 100% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Integrated circuit design
analog and mixed-signal circuits |
0.0 | 1 | 1980 | An NMOS Microcomputer Peripheral Interface Unit Incorporating an Analog-to-Digital Converter · IEEE Trans. Computers 1980 |
Integrated circuit design › analog and mixed-signal circuits › data converters
analog-to-digital converter |
0.0 | 1 | 1980 | An NMOS Microcomputer Peripheral Interface Unit Incorporating an Analog-to-Digital Converter · IEEE Trans. Computers 1980 |
Integrated circuit design › semiconductor devices
MOS technology |
0.0 | 1 | 1980 | An NMOS Microcomputer Peripheral Interface Unit Incorporating an Analog-to-Digital Converter · IEEE Trans. Computers 1980 |
Methods — techniques the papers use, named apart from their topics
constant slope conversion · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1980 | An NMOS Microcomputer Peripheral Interface Unit Incorporating an Analog-to-Digital ConverterabstractA peripheral interface unit for a microcomputer control system fabricated by a standard n-channel silicon-gate enhancement/ depletion MOS process is described. This unit can accept analog and digital inputs, generate pulse outputs, and multiply. The analog input capability is made possible by an on-chip A/D converter using a constant slope approach with an external capacitor. This converter can perform a 10 bit conversion in 5 ms and has an input voltage range of 0-5 V with only one 8 V power supply for the analog circuits. The die area required by the converter is small and the precision analog specifications needed for the process and devices are few. The die area of the converter is 3 mm2, out of a total unit area of 35 mm2. Tsuneo Funabashi, Katsuaki Takagi, Toshiro Tsukada, Hideo Nakamura, Michio Hara |
IEEE Trans. Computers | 2 |