Instruction cache performance is very important to instruction fetch efficiency and overall processor performance. The layout of an executable has a substantial effect on the cache miss rate during execution. This means that the performance of an executable can be improved significantly by applying a code-placement algorithm that minimizes instruction cache conflicts. We describe an algorithm for procedure placement, one type of code-placement algorithm, that significantly differs from previous approaches in the type of information used to drive the placement algorithm. In particular we gather temporal ordering information that summarizes the interleaving of procedures in a program trace. Our algorithm uses this information along with cache configuration and procedure size information to better estimate the conflict cost of a potential procedure ordering. We compare the performance of our algorithm with previously published procedure-placement algorithms and show noticeable improvements in the instruction cache behavior.

Many important protocols, such as Q.2931 or any protocol based on the ASN.1 basic encoding rules, are transmitted using tagged message formats, in which a message can be considered as a sequence of interleaved tag and data fields, where tag fields define the meaning of subsequent fields. These messages are computationally expensive to decode, partly because decoding each data field requires resting one or more tag fields. Evidence suggests that in some applications, although the potential space of message encodings may be very large, only a small number of message layouts are seen frequently, and thus some of the work required in decoding can be amortized over many messages. This paper analyzes the use of run-time code generation to generate optimized decoding instruction sequences for received messages matching previously observed layouts, and describes a prototype system that applies the techniques to decoding the Q.2931 and ASN.1 BER protocols. In the average case, substantial performance gains are seen.

Many techniques have been discovered to improve performance of bulk data transfer protocols which use large messages. This paper describes a technique that improves protocol performance for protocols that use small messages, such as signalling protocols, by reducing memory system penalties. Detailed measurements show that for TCP, most memory system costs are due to poor locality in the protocol code itself, rather than movement of data. We present a new technique, analogous to blocked matrix multiplication, for scheduling layer processing to reduce memory system costs, and analyze its performance in a synthetic environment.

This paper presents three new results concerning credit-based flow control for ATM networks: (1) a simple and robust credit update protocol (CUP) suited for relatively inexpensive hardware/software implementation; (2) automatic adaptation of credit buffer allocation for virtual circuits (VCs) sharing the same buffer pool; (3) use of credit-based flow control to improve the effectiveness of statistical multiplexing in minimizing switch memory. These results have been substantiated by analysis, simulation and implementation.