There is a growing demand for high-reliability and high-quality integrated circuit (IC) products, while their test costs should be kept as low as possible. We investigate the test process of advanced memory chips, where the high temperature operating life (HTOL) test has been used to determine their intrinsic reliability. This high temperature sampling test can run from 168 to 1,000 hours, so it is time-consuming and expensive. Recently, machine learning (ML) algorithms have been used to solve classification problems, so far as good training data can be obtained. In our case, there is already a large amount of parametric test data generated from the existing test flow. Therefore, in this work, we propose a decision tree (DT)-based screening method to predict weak (unreliable) dies that would fail the HTOL test. We show that experienced test engineers can prioritize the parametric test data for better use of the DT model. Finally, we take advantage of the high interpretability of DT to develop the multi-feature heuristics, which can be used to improve the quality of final test (FT). Keeping the overkill rate at 0%, our heuristics can screen out 25% more bad dies, i.e., we can improve the FT quality without additional cost.

with the increasing demand for safety-critical products, the quality and reliability of semiconductor components are among the top priorities. In recent years, test data analytics by machine learning (ML) algorithms are widely considered to have great potential for improving the quality and reliability of semiconductor chips. In this work, we inspect a typical test flow of advanced semiconductor products, and propose an ML-based weak die screening method for improving the quality and reliability of shipped products. We propose the feature prioritized random forest (FPRF) model, which can fit smoothly into the existing test flow. We perform experiments on an advanced SRAM product using the FPRF model. We perform feature analysis based on the test data obtained from the final test (FT). After the FPRF screening, we are able to screen out more bad dies from those that have passed the FT. For an overkill rate of 12.93 %, the bad die hit rate can be as high as 96.55%. One can explore the FPRF model for other products as well.

There is a growing demand for high-reliability and high-quality integrated circuit (IC) products, while their test costs should be kept as low as possible. We investigate the test process of advanced memory chips, where the high temperature operating life (HTOL) test has been used to determine their intrinsic reliability. This high temperature sampling test can run from 168 to 1,000 hours, so it is time-consuming and expensive. Recently, machine learning (ML) algorithms have been used to solve classification problems, so far as good training data can be obtained. In our case, there is already a large amount of parametric test data generated from the existing test flow. Therefore, in this work, we propose a decision tree (DT)-based screening method to predict weak (unreliable) dies that would fail the HTOL test. We show that experienced test engineers can prioritize the parametric test data for better use of the DT model. Finally, we take advantage of the high interpretability of DT to develop the multi-feature heuristics, which can be used to improve the quality of final test (FT). Keeping the overkill rate at 0%, we can screen out 25% more bad dies in the 5nm SRAM case with the heuristics, and in the 4nm case, we can screen out 14% more bad dies, i.e., we can improve the FT quality without additional cost.

Integrated passive devices (IPDs) have been widely used in advanced packaging of semiconductor chips, to improve their power integrity and impedance matching. There is a growing demand in guaranteeing signal and power integrity for the chips used in safety-critical products, such as those used in automotive, aviation, industrial, and defense systems, where IPDs help improve quality and reliability of the chips. Therefore, IPD testing and screening itself is essential. Note that the cost of replacing failed IPDs is much higher than the cost of manufacturing them, so screening bad IPDs before mounting is also crucial. In this work, we propose a machine learning (ML) based screening methodology to identifying the IPDs that have potential reliability issues. Based on the parametric data of 360,000 IPDs collected from the wafer probing test, the proposed Semiconductor Quality Net (SQnet) is trained to predict the IPDs which have low breakdown voltage, i.e., low reliability. Keeping the overkill rate below 10%, our method can screen out 6 to 15X more bad dies than the existing industrial methods, i.e., DPAT and GDBC.

Integrated passive devices (IPDs) have been widely used in advanced packaging of semiconductor chips, to improve their power integrity and impedance matching. There is a growing demand in guaranteeing signal and power integrity for the chips used in safety-critical products, such as those used in automotive, aviation, industrial, and defense systems, where IPDs help improve quality and reliability of the chips. Therefore, IPD testing and screening itself is essential. Note that the cost of replacing failed IPDs is much higher than the cost of manufacturing them, so screening bad IPDs before mounting is also crucial. In this work, we propose a machine learning (ML) based screening methodology to identifying the IPDs that have potential reliability issues. Based on the parametric data of 360,000 IPDs collected from the wafer probing test, the proposed Semiconductor Quality Net (SQnet) is trained to predict the IPDs which have low breakdown voltage, i.e., low reliability. Keeping the overkill rate below 10%, our method can screen out 6 to 15X more bad dies than the existing industrial methods, i.e., DPAT and GDBC.