Demo Data from EDBT 2026 / reviewers in the wild / expert
J. A. Gandhi
dblp:72/4188
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 1989
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 67% Hardware reliability and fault tolerance · 33% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › physical design › routing
channel routing |
0.0 | 1 | 1989 | DTR: A Defect-Tolerant Routing Algorithm · DAC 1989 |
Hardware reliability and fault tolerance
defect tolerance |
0.0 | 1 | 1989 | DTR: A Defect-Tolerant Routing Algorithm · DAC 1989 |
Electronic design automation
physical design |
0.0 | 1 | 1989 | DTR: A Defect-Tolerant Routing Algorithm · DAC 1989 |
Methods — techniques the papers use, named apart from their topics
channel routing algorithm · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1989 | DTR: A Defect-Tolerant Routing AlgorithmabstractA new channel routing algorithm called DTR (Defect-Tolerant Routing) is investigated. This algorithm minimizes the total area and simultaneously maximizes the performance by reducing the critical area which can potentially be the source of logical faults caused by the bridging effects of spot defects. Experimental results show DTR produces less critical area than Yoshimura&Kuh's algorithm [1]. Anucha Pitaksanonkul, Suchai Thanawastien, Chidchanok Lursinsap, J. A. Gandhi |
DAC | 4 |