Demo Data from EDBT 2026 / reviewers in the wild / expert
Bao-Chyn Liu
dblp:72/4262
· DBLP profile ↗
2ranked-venue papers
0as first author
0since 2021 · last 1989
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Memory systems · 46% Performance modeling and evaluation · 46% Interconnection networks and networks-on-chip · 7% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Memory systems
cache coherence |
0.0 | 1 | 1989 | Analysis and Comparison of Cache Coherence Protocols for a Packet-Switched Multiprocessor · IEEE Trans. Computers 1989 |
Memory systems › cache coherence
cache coherence protocol |
0.0 | 1 | 1989 | Analysis and Comparison of Cache Coherence Protocols for a Packet-Switched Multiprocessor · IEEE Trans. Computers 1989 |
Performance modeling and evaluation › queueing models
mean value analysis |
0.0 | 1 | 1989 | Analysis and Comparison of Cache Coherence Protocols for a Packet-Switched Multiprocessor · IEEE Trans. Computers 1989 |
Performance modeling and evaluation
queueing models |
0.0 | 1 | 1989 | Analysis and Comparison of Cache Coherence Protocols for a Packet-Switched Multiprocessor · IEEE Trans. Computers 1989 |
Interconnection networks and networks-on-chip › bus-based interconnection
shared bus |
0.0 | 1 | 1989 | Analysis and Comparison of Cache Coherence Protocols for a Packet-Switched Multiprocessor · IEEE Trans. Computers 1989 |
Methods — techniques the papers use, named apart from their topics
mean value analysis · 0.0analytical modeling · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1989 | Analysis of MIN Based Multiprocessors with Private Cache Memories
Laxmi N. Bhuyan, Bao-Chyn Liu, Irshad Ahmed |
ICPP (1) | 2 |
| 1989 | Analysis and Comparison of Cache Coherence Protocols for a Packet-Switched MultiprocessorabstractAnalytical models are developed for seven existing cache protocols, namely, Write-Once, Write-Through, Synapse, Berkeley, Illinois, Firefly, and Dragon. The protocols are implemented on a multiprocessor with a packet-switched shared bus. The models are based on queuing networks that consist of both open and closed classes of customers. The models incorporate the requests for invalidation signals, write-through, and write-back operations, and the solution is based on the mean value analysis (MVA) algorithm. The performance of these protocols under various system parameters is compared on the basis of the models. It is found that Firefly and Dragon perform better than the others.> Qing Yang 0001, Laxmi N. Bhuyan, Bao-Chyn Liu |
IEEE Trans. Computers | 3 |