In this work, we present a FPGA-based Generalized Hough Transform custom processor to calculate similarities between arbitrary shapes. Raw data are 44 × 36 DC images extracted directly from low-resolution compressed video (352 × 288). The outputs are two numbers per frame that quantify the image similitude in terms of scale and rotation. The proposed architecture efficiently resolves the detection of pixel pairs, and the voting of distances and rotations, without memory access conflicts. These operations are inherent to Hough transformation. The paper condenses some circuit solutions suitable to hardwiring video processing. They take full advantage of using small embedded memories as look-up tables. The complete processor is validated with benchmark video samples that cover different scenarios and problems: sport, drama, and news. The final version internally operates at 100 MHz and fits inside a small FPGA chip. The highly concurrent architecture employs both pipelining and parallelism using hardware replication. The final performance is over 40 Giga fixed-point operations per second.

Constant multipliers are widely used in signal processing applications to implement the multiplication of signals by a constant coefficient. However, in some applications, this coefficient remains invariable only during an interval of time, and then, its value changes to adapt to new circumstances. In this article, we present a self-reconfigurable constant multiplier suitable for LUT-based FPGAs able to reload the constant in runtime. The pipelined architecture presented is easily scalable to any multiplicand and constant sizes, for unsigned and signed representations. It can be reprogrammed in 16 clock cycles, equivalent to less than 100 ns in current FPGAs. This value is significantly smaller than FPGA partial configuration times. The presented approach is more efficient in terms of area and speed when compared to generic multipliers, achieving up to 91% area reduction and up to 102% speed improvement for the case-study circuits tested. The power consumption of the proposed multipliers are in the range of those of slice-based multipliers provided by the vendor.

In this paper, an optimization for the classical statistical power estimation method is proposed. This technique is applied to the individual nodes. The optimization is based on two observations. Firstly, a small percentage of both the nodes and the estimated power requires nearly a half of the total simulation time. On the other hand, the statistical method produces results with better accuracy than those specified by the user. This additional precision enables to reduce the run time for the slow convergence nodes with no loss of accuracy. A simple partitioning of the nodes into two groups, A and B, with normal and high computational cost respectively, leads to a modified stopping criterion with dramatic savings in the run time.

This article presents a power estimation tool integrated with an FPGA design flow. It is able to estimate total and individual-node average power consumption for combinational blocks. The tool is based on the statistical approach, allowing the user to specify the tolerated error and confidence level of the power estimation. An important feature of this software is the short pulse filtration that leads, in other case, to overestimation. Power maps generation is implemented to help both to detect hot-spots, and perform a power optimization. These maps show the power at every physical position in the die. Several circuits have been tested in order to demonstrate the tool features and usability. The estimated values of dynamic power have been compared with physical measurements for Virtex and Virtex-E devices.

This paper shows a method to verifying the thermal status of complex FPGA-based circuits like microprocessors. Thus, the designer can evaluate if a particular block is working beyond specifications. The idea is to extract the output frequencies of an array of ring-oscillators previously distributed in the die, taking full advantage of the configuration port capabilities in Xilinx technology. As a result, it is shown that the FPGA technology offers the designers of embedded systems the possibility of viewing a detailed thermal map of a circuit at a minimum cost. The verification can be done in actual working conditions; for example with heat sinks and fans attached to the chip, inside the system case, or even in an on-board satellite application. The main results of the work are unthinkable using other alternatives like IR cameras, external sensors, or embedded diodes.

A power estimation tool for FPGA technology was developed. The current version is able to estimate total and individual node average power consumption in combinational blocks. The tool is statistical-based, allowing the user to specify the tolerated error for a given confidence level. Due to the fact that the power for individual nodes can be obtained, the software is able to connect this information with the physical positions of the nodes. In order to demonstrate the tool features and usability, a set of arithmetic blocks for digital radio have been utilized as benchmark circuit. Main results have been compared with actual power measurements for Virtex and Virtex-II devices.

Wave pipelining offers a unique combination of high speed, low latency, and moderate power consumption. The construction of wave pipelines is benefited by the use of gates and buffers with data-independent delays and the knowledge of the interconnection delays. These two features are present in several SRAM-based field programmable gate arrays (FPGA's): look-up tables (LUT's) allow the designer to mask the delay of different gates and combinational functions, and the timing characteristics of each wire segment are a priori known. This work describes a set of experiments about wave pipelining on FPGA's. The results show that a 13-LUT logic depth circuit mapped on an XC4005PC84-6 runs as high as 85 MHz (single phase clocking) or 80 MHz (intentionally skewed clocking), exhibiting a latency of 95 ns. This high throughput/latency ratio is unattainable using classic pipelining.

No abstract available.