The use of formal models of computation in dealing with increasing complexity of embedded systems design is gaining attention. A successful model of computation must be able to handle both control-dominated and data-dominated behaviors, which are most often simultaneously present in complex embedded systems. Besides behavioral heterogeneity, direct support for modeling distributed systems is also desirable, since an increasing number of embedded systems belong to this category. In this paper, we present distributed DFCharts (DDFCharts), a language based on a formal model that targets distributed heterogeneous embedded systems. Its top hierarchical level is made suitable to capture distributed systems. Behavioral heterogeneity is addressed by composing finite-state machines (FSMs) and synchronous dataflow graphs (SDFGs). We illustrate modeling in DDFCharts with practical examples and describe its implementation on heterogeneous target architecture.

Single-clock specifications with purely synchronous communication have been successfully used in capturing the behavior of small and medium scale embedded systems. In large scale embedded systems, where processes often operate at vastly different speeds, using a single clock in an entire specification can be difficult. In this paper, we present Multiclock Charts (McCharts), a language where finite state machines driven by different clocks are composed. The communication between FSMs is specified by both synchronous and asynchronous mechanisms. The essential feature in the semantics of McCharts is that a complete specification can be mapped onto a single multiclock FSM (MCFSM).

In this paper, we propose a new system-level design language, called SystemJ. It extends Java with synchronous reactive features present in Esterel and asynchronous constructs suitable for modelling globally asynchronous locally synchronous systems. The strength of SystemJ comes from its ability to offer the data processing and encapsulation elegance of Java, Esterel-like reactivity and synchrony, and the asynchronous de-coupling of CSP all within the Java framework. Using standard Java environments, for specification and modelling, or specialised reactive embedded processors, for high performance implementation, the SystemJ design flow is extremely versatile. With the increasing attention that Java gets in embedded systems, SystemJ comes to address data and control, software and hardware, modelling and implementation in a unified manner

Specification of embedded systems based on formal models of computation is gaining importance. The behavior of an increasing number of embedded systems is heterogeneous, consisting of a mixture of control-dominated and data-dominated parts. While models of computations suitable to control-dominated systems and data-dominated systems are well developed, there are only a limited number of models catering to both systems. In this paper, we present informally a new model for heterogeneous embedded systems, called HEMOC, which combines three common models of computation, synchronous reactive, hierarchical finite state machines and synchronous data flow. Then, the languages Esterel and SyncCharts are used for system specification following the new model in order to determine what they need to become suitable specification platform.