The yield of ICs has always been crucial to the commercial success of their manufacture. One solution to the low yield problem is to improve the manufacturing and testing processes. This is very costly and quite difficult to implement. The practical approach is to use a fault-tolerant design. In this paper, a design of repairable and fully diagnosable folded PLA is presented, in which the defects can be repaired with-out reconfiguring the external routing. The design achieves a full diagnosability of single and multiple stuck-at, bridging, and crosspoint faults, and has led to a significant yield improvement. The physical layout and floor plan are also provided to assess the chip area.

The yield of ICs is crucial to the commercial success of their manufacture. One practical solution to the low yield problem is the use of fault-tolerant design. A fault diagnosable and repairable PLA design has been proposed to detect, locate, and repair faults, and has led to a significant yield improvement. An alternated defect-tolerant design of PLAs with folding technique is presented to further improve chip yield. The proposed design achieves full diagnosability of stuck-at, bridging, and crosspoint faults during the manufacturing process, and provides full testability after the chip is packaged.>