This paper presents an application of advanced first-order second-moment (AFOSM) reliability method to probabilistic design of integrated circuits with correlated parameters. The method avoids the transformation to the space of uncorrelated parameters and provides a conservative estimate of the yield. Optimal nominal values are found such that the cost of tolerances is minimized while the desired yield is achieved. Numerical results are presented for a switched capacitor filter and verified by Monte Carlo simulation.

The paper describes a program for fast simulation of nonlinear switched analog networks used in communications and power electronics. The switches act as open and short circuits and are used to model switching diodes, transistors or thyristors. At switching instants, the values from left and right are obtained, even in case of inconsistent initial conditions.

The aim of this forum session is to stimulate a discussion and an exchange of ideas on the advantages and disadvantages of symbolic analysis. The focus of the discussion is on the feasibility of the symbolic approaches in circuit design and the role they can and/or cannot play in the circuit CAD world.>

A class of graphs with circulant blocks, i.e. graphs which can be decomposed into circulant subgraphs, is considered. A closed form formula for eigenvalues of the decomposed graph in terms of eigenvalues of partition subgraphs is given. Decomposition into two layer graph is distinguished as the most computationally effective case. A formula for counting spanning trees in graphs with circulant blocks, based on eigenvalues, is introduced. Illustrative examples test the method.>

A method for constraint region approximation, design centering and yield estimation is introduced. Extreme points of the constraint region are identified by inscribing into it the largest possible ellipsoid. Ellipsoid center is the point that centers the design. Ellipsoidal, polytope and second order Taylor series approximation schemes to the constraint region are discussed. Accuracy and implementation of the method are outlined. Two examples testing the method are included and applications to centering, tolerancing and yield estimation are shown.>

A novel accelerated computer oriented procedure, based on the Newton method, is presented to determine the steady-state response of linear networks with internally and/or externally controlled switches. The Jacobian matrix is computed concurrently with the time-domain response for all possible switching times with the initial conditions. The circuit response may be discontinuous and Dirac impulses are permitted at the switching instants. Several examples show the speed and accuracy of the method.>

The authors describe a high-level functional analog simulator for hybrid logic/analog networks. it forms one level of an experimental multilevel simulation system which is currently under development. The functional simulator is described in detail, and the structure of the multilevel simulator is briefly outlined. It can be used as a stand-alone system but was developed specifically for coupling with other levels of simulation which also use time responses (or voltage waveforms). Since Boolean algebra cannot operate with time responses, a new algebra is developed. It eliminates the unknown state, the main obstacle in coupling analog simulation to logic simulation. Logic states are replaced by operations on time functions, in this case represented by piecewise linear segments. High-level analog operations are also possible. The simulator based on these ideas was used to solve several high-level analog problems. The examples presented demonstrate its application.>

It is an accepted practice in signal delay estimation to model MOS digital circuits as RC circuits. In most cases Elmore's definition is exactly equivalent to the group delay of the network at zero frequency. A computationally efficient noniterative method to calculate this delay for networks with any linear elements and arbitrary topology is presented. It is shown that in RC networks under certain conditions, the Elmore delay and the 50% unit step response delay are related by a constant which is largely independent of the element values and topology. An efficient method to obtain sensitivities of the delay with respect to any element in the network is presented.>

A switch-level logic simulator for MOS networks based on the theory of current-limited switches is described. It was derived from a switch-level timing simulator by suppressing time-related information and by eliminating invalid events. The simulator obeys Kirchoff's laws and after initialization every node has a known voltage. It can thus be used to drive analog simulation. Fault simulation is easily incorporated by representing the line-open fault by an open circuit and the node-short fault by a short circuit. Examples demonstrate application to both logic and fault simulation.>

The approximation of MOSFET nonlinearities by use of polynomial splines was investigated for reducing both circuit model development time and model simulation cost. After a brief tutorial on spline functions, it is shown how the number of independent variables for the MOSFET simulation models in digital circuits is reduced by their use. A tableau formulation for generating splines is presented along with a storage-reduction technique for polynomial spline coefficients. Mathematical programming problems for one-, two-, and three-dimensional splines are given that result in accurate monotonic splines using few segments. Two spline segments are shown to provide sufficient accuracy in the one-dimensional case, while 4*4 and 2*5*5 segments provide sufficient accuracy in the two- and three-dimensional cases, respectively.>

A description is given of NETOPT, an interactive program for multiobjective design of linear networks with emphasis on RC active filters. The program section consists of four parts: the analysis program, an optimizer specially designed for network applications, an interface which allows multiobjective minimization, and a part with miscellaneous support functions. After noting the need to control group delay, a theory is developed for efficient calculation of group delay and its derivatives with respect to circuit elements along with a theory of design centering for filters. The optimization interface is then described in detail and three design examples that used the program are provided.>

An algorithm for switch-level timing simulation of MOS logic networks is proposed. The event-driven simulator, WATSWITCH, partitions the circuit into subblocks which are solved by replacing each transistor by a special current-limited switch. Because of the choice of the switch model, time-domain responses are obtained without model evaluations during the simulation, without table lookup, and without time-domain integration. This is achieved by allowing only capacitors and piecewise-constant current sources to be the elements of the simulator. Because resistors are not allowed, the time responses are known to be piecewise-linear segments. As a consequence, neither numerical integration nor transistor model evaluation is needed during the simulation.>

A nonlinear constrained optimizer, WATOPT, targeted towards circuit applications is described. It utilizes a specially tailored quadratic program which reduces storage requirements and improves speed of computations. Three advanced designs in the frequency domain show application.