Demo Data from EDBT 2026 / reviewers in the wild / expert
David J. Walkey
dblp:72/5470
· DBLP profile ↗
3ranked-venue papers
2as first author
0since 2021 · last 2004
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 2 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
3 papers |
Electronic design automation · 26% Energy-efficient computing · 25% Integrated circuit design · 19% |
Topics — the 6 heaviest of 8, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Energy-efficient computing
thermal modeling |
0.1 | 2 | 2004 | Compact, netlist-based representation of thermal transient coupling using controlled sources · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2004 A simplified model for the effect of interfinger metal on maximum temperature rise in a multifinger bipolar transistor · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2003 |
Integrated circuit design
semiconductor device modeling |
0.1 | 2 | 2004 | A simplified model for the effect of interfinger metal on maximum temperature rise in a multifinger bipolar transistor · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2003 Compact, netlist-based representation of thermal transient coupling using controlled sources · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2004 |
Hardware reliability and fault tolerance › integrated circuit reliability
self-heating |
0.0 | 1 | 2003 | A simplified model for the effect of interfinger metal on maximum temperature rise in a multifinger bipolar transistor · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2003 |
Performance modeling and evaluation › simulation › thermal simulation
3d thermal simulation |
0.0 | 1 | 2001 | A 3D thermal simulation tool for integrated devices-Atar · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2001 |
Electronic design automation
mesh generation |
0.0 | 1 | 2001 | A 3D thermal simulation tool for integrated devices-Atar · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2001 |
Performance modeling and evaluation › simulation
thermal simulation |
0.0 | 1 | 2001 | A 3D thermal simulation tool for integrated devices-Atar · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2001 |
Methods — techniques the papers use, named apart from their topics
electrical dual-circuit topology · 0.0controlled sources · 0.0segmented emitter model · 0.0lumped thermal model · 0.0transmission line matrix method · 0.0resistance-capacitance network extraction · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2004 | Compact, netlist-based representation of thermal transient coupling using controlled sourcesabstractA compact, efficient electrical dual-circuit topology for the representation of transient thermal coupling is presented. Based on controlled sources, the method allows an arbitrary level of complexity to be used for each self and coupled response. Two possible variations on the circuit form, and the resulting requirements for model extraction, are developed. The method is applied to the modeling of transient thermal self-heating and coupling data for a pair of thermal sources representative of integrated device structures in semi-infinite homogeneous as well as trench-isolated substrates. David J. Walkey, Tom J. Smy, Dritan Celo, Tom W. MacElwee, Michael C. Maliepaard |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |
| 2003 | A simplified model for the effect of interfinger metal on maximum temperature rise in a multifinger bipolar transistorabstractThe prediction of a simple lumped representation of heat sharing through emitter interconnect in high-power multiemitter bipolar devices is compared to numerical thermal simulation and found to exhibit nonphysical results. Using numerical simulation, interfinger metal heat flow is characterized qualitatively in three dimensions and the requirements for a more accurate model are determined. A new modeling approach based on these insights, using segmented emitters and a coarse representation of the metal structure, yields results within 2% of those obtained from numerical thermal simulation for a wide variety of device geometries and substrate materials, with a simulation time reduction of more than an order of magnitude. Using the new model, an extensive series of simulations is performed for devices fabricated in Si, GaAs, and InP substrates using Al and Au for metallization. Reduction in maximum temperature due to the presence of emitter interconnect in these structures is found to be in the range of 5%-15%. David J. Walkey, Dritan Celo, Tom J. Smy |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |
| 2001 | A 3D thermal simulation tool for integrated devices-AtarabstractThis paper presents a novel three-dimensional (3D) thermal simulation tool for semiconductor integrated devices. The simulator is used to automatically generate an accurate 3D physical model of the device to be simulated from layout information. The simulator produces an appropriate mesh of the device based on a rectangular block structure. The mesh is automatically created such that a fine mesh is produced around heat generation regions, but a moderate number of blocks are used for the entire device. This paper first confirms that the simulator produces an accurate solution to the nonlinear differential equation describing the heat flow. Then model generation from three example technologies (silicon trench, GaAs mesa structures, silicon on insulator) is presented. The potential of the simulator to quickly and easily explore the effect of layout and process variations is illustrated, with the simulation of a two-transistor GaAs power cell as a large example. The program incorporates a transient solver based on a transmission line matrix (TLM) implementation using a physical extraction of a resistance and capacitance network. The formulation allows for temperature dependent material parameters and a nonuniform time stepping. An example of a full transient solution of heat flow in a realistic Si trench device is presented. Tom J. Smy, David J. Walkey, Steven K. Dew |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 2 |