Demo Data from EDBT 2026 / reviewers in the wild / expert
Seongkyun Shin
dblp:72/5702
· DBLP profile ↗
3ranked-venue papers
1as first author
0since 2021 · last 2004
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Electronic design automation · 100% |
Topics — the 6 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
hardware verification and test |
0.1 | 2 | 2004 | A decoupling technique for efficient timing analysis of VLSI interconnects with dynamic circuit switching · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2004 Generalized traveling-wave-based waveform approximation technique for the efficient signal integrity verification of multicoupled transmission line system · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2002 |
Electronic design automation
interconnect modeling |
0.1 | 2 | 2004 | A decoupling technique for efficient timing analysis of VLSI interconnects with dynamic circuit switching · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2004 Generalized traveling-wave-based waveform approximation technique for the efficient signal integrity verification of multicoupled transmission line system · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2002 |
Electronic design automation › timing analysis
dynamic timing analysis |
0.0 | 1 | 2004 | A decoupling technique for efficient timing analysis of VLSI interconnects with dynamic circuit switching · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2004 |
Electronic design automation › hardware verification and test
timing verification |
0.0 | 1 | 2004 | A decoupling technique for efficient timing analysis of VLSI interconnects with dynamic circuit switching · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2004 |
Electronic design automation › signal integrity
crosstalk analysis |
0.0 | 1 | 2002 | Generalized traveling-wave-based waveform approximation technique for the efficient signal integrity verification of multicoupled transmission line system · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2002 |
Electronic design automation › signal integrity
signal integrity verification |
0.0 | 1 | 2002 | Generalized traveling-wave-based waveform approximation technique for the efficient signal integrity verification of multicoupled transmission line system · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2002 |
Methods — techniques the papers use, named apart from their topics
effective capacitance and inductance · 0.0decoupling technique · 0.0SPICE simulation · 0.0traveling-wave-based waveform approximation · 0.0eigen-mode decoupling · 0.0dominant pole approximation · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2004 | A decoupling technique for efficient timing analysis of VLSI interconnects with dynamic circuit switchingabstractIn today's high-speed/high-density very large scale integrated (VLSI) circuit designs with coupled interconnect lines, signal transients are strongly correlated with the input switching patterns. Signal-delay variations due to the input-switching patterns may be more than /spl plusmn/50% of the delay of an isolated single line. Thus, blind static timing-analysis techniques without consideration of the detailed switching effects may not be accurate enough to meet tight timing margins for today's deep submicron (DSM)-based VLSI circuits. In this paper, the signal-transient responses of multicoupled interconnect lines due to various input-switching patterns are analyzed in terms of the effective capacitances and effective inductances. Thereby, the critical delay line of multicoupled interconnect lines is decoupled into an effective single-isolated line. With the proposed novel decoupling technique for multicoupled interconnect lines, the accurate dynamic delay of strongly coupled interconnect lines can be readily determined with physical layout information. For example, in switching patterns, the paper shows that the signal delays calculated by using the effective single-line models have excellent agreement with SPICE simulations using the generic coupled interconnect circuit models. That is, the accuracy for both RC-dominant lines and RLC lines is within 10% error (but often within 5% error). Thus, without any significant modification of existing IC computer-aided design frameworks, the technique can be directly as well as usefully employed for accurate timing verification of DSM-based VLSI designs. Yungseon Eo, Seongkyun Shin, William R. Eisenstadt, Jongin Shim |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 2 |
| 2004 | Analytical models and algorithms for the efficient signal integrity verification of inductance-effect-prominent multicoupled VLSI circuit interconnectsabstractNovel signal integrity verification models and algorithms for inductance-effect- prominent RLC interconnect lines are developed by using a traveling-wave-based waveform approximation (TWA) technique. The multicoupled line responses are decoupled into the eigenmodes of the system in order to exploit the TWA technique. Then, the response signals are mathematically represented by the linear combination of each eigenmode response based on TWA, followed by reporting the signal integrity models and algorithms for the multicoupled lines. The signal integrity of VLSI circuit interconnects is complicatedly correlated with input signal switching-patterns, layout geometry, and termination conditions. It is shown that the technique can be efficiently employed for complicated multicoupled interconnect lines with various termination conditions and the signal transients based on the technique have excellent agreement with SPICE simulations. Thus, with the proposed technique, the switching-dependent signal delay, crosstalk, ringing, and glitches of the inductance-effect-prominent RLC interconnect lines can be accurately as well as efficiently determined. Seongkyun Shin, Yungseon Eo, William R. Eisenstadt, Jongin Shim |
IEEE Trans. Very Large Scale Integr. Syst. | 1 |
| 2002 | Generalized traveling-wave-based waveform approximation technique for the efficient signal integrity verification of multicoupled transmission line systemabstractAs very large scale integration (VLSI) circuit speed rapidly increases, the inductive effects of interconnect lines strongly impact the signal integrity of a circuit. Since these inductive effects make the signal integrity problems much more serious as well as intricate, they become one of the critical issues in today's high-speed/high-density VLSI circuit design. In this paper, a generalized traveling-wave-based waveform approximation (TWA) technique is presented which can be accurately as well as efficiently employed for the signal integrity verification of the inductively dominated (moderate Q) multicoupled RLC transmission line system. The technique is composed of three steps. First, the signals in the multicoupled (n-coupled) transmission line system are decoupled into n-isolated eigen-modes (i.e., basis vectors). Next, the slow-transient low-frequency characteristics of the system response are determined, approximately, in the frequency-domain by using the dominant poles of the basis vectors. Finally, the fast-transient high-frequency characteristics of the system response are calculated in the time domain by using the traveling wave characteristics of the basis vectors. It is shown that the time-domain responses of the multicoupled RLC transmission line system can be accurately as well as efficiently modeled with the generalized TWA technique. Then, in inductance-dominant multicoupled interconnect networks, switching-dependent signal integrity, i.e., signal delay, crosstalk, ringing, and glitches are investigated extensively with the proposed technique. Yungseon Eo, Seongkyun Shin, William R. Eisenstadt, Jongin Shim |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 2 |