The Realizer, is a logic emulation system that automatically configures a network of field-programmable gate arrays (FPGAs) to implement large digital logic designs, is presented. Logic and interconnect are separated to achieve optimum FPGA utilization. Its interconnection architecture, called the partial crossbar, greatly reduces system-level placement and routing complexity, achieves bounded interconnect delay, scales linearly with pin count, and allows hierarchical expansion to systems with hundreds of thousands of FPGA devices in a fast and uniform way. An actual multiboard system has been built, using 42 Xilinx XC3090 FPGAs for logic. Several designs, including a 32-b CPU datapath, have been automatically realized and operated at speed. They demonstrate very good FPGA utilization. The Realizer has applications in logic verification and prototyping, simulation, architecture development, and special-purpose execution.>

The Realizer, a system which automatically configures a network of field-programmable gate arrays (FPGAs) to implement large digital logic designs, is presented. Logic and interconnect are separated to achieve optimum FPGA utilization. The interconnection architecture, called the partial crossbar, greatly reduces system-level placement and routing complexity, achieves bounded interconnect delay, scales linearly with pin count, and allows hierarchical expansion to systems with hundreds or thousands of FPGA devices in a fast and uniform way. An actual multiboard system has been built, using 42 XC3090 FPGAs for logic. A 32-b CPU datapath has been automatically realized and operated at speed, and demonstrates very good FPGA utilization.>

Most work on automating the translation of high-level microprogramming languages into microcode has dealt with lexical and syntactic analysis and the use of manually produced macro tables for code generation. We describe an approach to and some results on the formalization and automation of the more difficult problem of retargeting local code generation in a machine-independent, optimizing microcode synthesis system. Whereas this problem is similar in many ways to that of retargeting local code generation in high-level language compilers, there are some major differences that call for new approaches. The primary issues addressed in this paper are the representation of target microprogrammable machines, the intermediate representation of local microprogram function, and general algorithmic methods for deriving local microcode from target machine and microcode function specifications. Of particular interest are the use of formal semantics and data flow principles in achieving both a general and reasonably efficient solution. Examples of the modeling of a representative horizontal machine (the PUMA) and the generation of microcode for the PUMA machine model from our working implementation are presented.

We consider the complexity of the problem of encoding microoperations into the fields of a control word on a horizontally microprogrammed machine, and show it to be NP-complete. The major result of this correspondence is a formalization of the microinstruction encoding problem, which makes the complexity argument straightforward.

A semantics based scheme for use in machine-independent microprogram synthesis is described. The input to the synthesis system consists of a micro-instruction set processor model and requirement specifications. Validity and transformation rules which are an integral part of the system are used in an attempt to prove the existence of a microprogram satisfying the requirements and if feasible such a microprogram can be extracted directly from the proof. The primary goal of this paper is to describe a system of validity and transformation rules for use in such a synthesis system.