As integration density increases, topology reconfiguration has emerged as a critical fault-tolerant technique for on-chip multiprocessors. To the best of our knowledge, existing methods for handling processor element (PE) faults in NoC-based multiprocessor arrays primarily target random faults, lacking effective strategies to handle clustered faults. To address this problem, this paper proposes a fast two-stage algorithm for constructing a high-performance, load-balanced logical topology. First, a diagonal-based fault replacement mechanism is introduced to minimize compensation paths for clustered faulty PEs. Second, an innovative candidate region selection strategy is proposed to replace faulty PEs, generating an initial topology with fewer row and column shifting operations. Finally, a novel Hawk-Tabu search algorithm is developed to further enhance communication performance through global search and local refinement of the logical topology. Experimental results show that, compared to state-of-the-art algorithms, the proposed approach reduces communication latency by an average of 10.01%, congestion by 10.37%, and fault-shifting hop count by 13.31% under a 64 × 64 topology with 7 × 7 clustered faults, while also achieving over 90% reduction in reconfiguration time. The proposed algorithms not only improve communication performance by alleviating latency and congestion issues but also enhance the efficiency of reconfiguration.

Fault-tolerant reconfiguration is essential for improving the reliability and efficiency of multiprocessor arrays. However, existing reconfiguration approaches primarily focus on algorithmic optimization, often neglecting architectural imbalance and communication bottlenecks arising from asymmetric redundancy placement. To overcome these limitations, this paper proposes an efficient framework that combines a novel double-sided redundant architecture with two-stage optimization algorithms to enhance interconnect efficiency under permanent processing element (PE) faults. The proposed$R_{l}+M+R_{r}$architecture symmetrically distributes redundant columns on both sides of the array while maintaining the same total number of spare PEs as single-sided redundancy, thereby mitigating unbalanced compensation paths and long communication distances without increasing hardware cost. Based on this structure, a shortest-path fault compensation algorithm is developed to minimize inter-PE communication distances, and a wide Tabu-based optimization algorithm is introduced as a second-stage refinement for global exploration and multi-directional reconfiguration. Experimental evaluations demonstrate that the proposed framework achieves superior communication performance and scalability compared with state-of-the-art methods under both single-sided and double-sided redundant architectures. It achieves lower latency, higher throughput, and reduced energy consumption while maintaining identical redundant resources and a smaller interconnect area footprint, confirming the efficiency and practicality of the proposed fault-tolerant topology reconfiguration strategy.

Three-dimensional (3-D) VLSI processor arrays offer high integration density and scalability, but their increasing system and interconnect complexity pose significant challenges to reliable reconfiguration under permanent hardware failures. Most existing reconfiguration approaches primarily target processing element (PE) faults and provide limited support for interconnect-related failures, such as switch and link faults, which can severely constrain feasible reconfiguration solutions and the achievable size of fault-free subarrays at the system level. This article investigates system-level fault-tolerant reconfiguration of reconfigurable 3-D VLSI processor arrays under multicomponent failures, including PE, switch, and link faults. We first analyze the system-level impact of different fault types and show that interconnect-level faults, especially switch failures, impose more pronounced constraints on reconfiguration effectiveness than PE faults. Based on this observation, a general plane-exclusion mechanism is introduced that can be integrated with representative PE-only reconfiguration schemes to enhance tolerance to switch and link failures. Furthermore, a fault-transformation preprocessing mechanism is developed to model switch failures as equivalent link disconnections, enabling unified system-level handling of heterogeneous faults and improving structural robustness. To mitigate excessive interconnect overhead introduced during reconfiguration, a long-interconnect optimization strategy is incorporated. Experimental results demonstrate that the proposed techniques significantly improve reconfiguration capability and scalability. In particular, the fault-transformation mechanism achieves over 90% of the theoretical upper bound in PE utilization under high switch fault densities, nearly doubling PE utilization compared with baseline methods, while the interconnect optimization reduces the number of long interconnects by more than 10% on average across all evaluated cases.

As the integration density of multiprocessor arrays increases, the likelihood of permanent faults in processing elements (PEs) rises, requiring effective topology reconfiguration for system reliability. However, existing router-based multiprocessor arrays reconfiguration methods predominantly rely on redundancy techniques and lack effective degradation strategies for applications of varying sizes. To address this, we propose a two-stage degradation-based topology reconfiguration algorithm to construct a maximized and high-performance logical array. First, we introduce a novel fault compensation mechanism by defining a set of faulty PE candidates to identify locally optimal fault-free PEs for compensation, minimizing the compensation path. Building upon this, we develop a greedy bidirectional column reconfiguration algorithm that constructs an initial fault-free logical array with short interconnects and prove its maximality. Lastly, we propose a satisfiability-based reconfiguration algorithm, transforming the topology reconfiguration problem into a satisfiability problem via a SAT model, reducing interconnect redundancy, and further optimizing array performance. Experimental results demonstrate that the proposed algorithm consistently outperforms state-of-the-art methods in reducing communication latency and alleviating link congestion, especially under high fault density conditions. Furthermore, as array size and fault density increase, the effectiveness of the proposed method becomes more pronounced, showcasing excellent scalability and robustness.

Background : Code-line-level bugginess identification (CLBI) is an important area within software quality assurance, aiming to pinpoint potential buggy source code lines in a given software product. Recently, two concurrent approaches, GLANCE and DeepLineDP, have showcased impressive performance by respectively leveraging syntactic and semantic features compared with the existing state-of-the-art (SOTA) approaches in this field. Problem : Yet, the literature lacks a thorough investigation that fuses these two types of features to enhance CLBI. Such fusion holds the promise of significantly improving the efficacy of identifying defective lines. Objective : We aim to advance CLBI by fusing syntactic and semantic features, thereby harnessing their respective strengths. Method : We propose to build a CLBI approach, booSting DeePLineDP wIth syntaCtic fEatures (SPLICE) , by fusing syntactic features from GLANCE and semantic features from DeepLineDP. SPLICE comprises three variants—SPLICE-S, SPLICE-G, and SPLICE-F—each utilizing a unique line-level sorting approach. We make a comprehensive comparison with the existing SOTA approaches using six performance metrics. Result : Through an analysis of nine open source projects, our experimental results reveal that SPLICE is competitive with current SOTA CLBI approaches. Notably, SPLICE-F demonstrates superiority over all SOTA CLBI approaches, including GLANCE and DeepLineDP, across all six metrics, indicating a substantial improvement. Conclusion : This discovery underscores the critical importance of future CLBI research in fusing syntactic and semantic features to construct more effective bugginess identification approaches. It is worth noting that the analysis was conducted within the context of Java programs, which highlights the potential for exploring similar methods in other programming languages in future research.

Abstract Background Software defect prediction (SDP) is a topic actively researched in the software engineering community. Within‐project defect prediction (WPDP) involves using labeled modules from previous versions of the same project to train classifiers. Over time, many defect prediction models have been evaluated under the WPDP scenario. Problem Data duplication poses a significant challenge in current WPDP evaluation procedures. Unchanged modules, characterized by identical executable source code, are frequently present in both target and source versions during experimentation. However, it is still unclear how and to what extent the presence of unchanged modules affects the performance assessment of WPDP models and the comparison of multiple WPDP models. Method In this paper, we provide a method to detect and remove unchanged modules from defect datasets and unveil the impact of data duplication in WPDP on model evaluation. Results The experiments conducted on 481 target versions from 62 projects provide evidence that data duplication significantly affects the reported performance values of individual learners in WPDP. However, when ranking multiple WPDP models based on prediction performance, the impact of removing unchanged instances is not substantial. Nevertheless, it is important to note that removing unchanged instances does have a slight influence on the selection of models with better generalization. Conclusion We recommend that future WPDP studies take into consideration the removal of unchanged modules from target versions when evaluating the performance of their models. This practice will enhance the reliability and validity of the results obtained in WPDP research, leading to improved understanding and advancements in defect prediction models.

Abstract Cross‐version defect prediction (CVDP) for evolutionary projects has attracted much attention from researchers in recent years. For multiple versions of an object‐oriented project, the degree of evolution (e.g., the degree of class change) between successive versions can reflect the differences between versions, which could affect the performance of CVDP. Therefore, how to measure the degree of evolution between successive versions and explore the correlations with the performance of CVDP are very important for software defect prediction. Based on the successive versions of evolutionary projects, this paper proposes six evolutionary measures from three aspects of class change, metric change, and label change, including the Ratio of New Classes (RNC), the Ratio of Deleted Classes (RDC), the Average Ratio of Metric Change (ARMC), the Ratio of Label Changed Classes (RLCC), the Ratio of Unchanged Classes (RUC), and the Ratio of Interference Classes (RIC). An empirical study was conducted on 40 versions of 11 object‐oriented projects from the PROMISE repository. Precision, Recall, F‐measure, and AUC were used as the performance indicators. Three correlation approaches (Pearson, Spearman, and Kendall) are applied to show the correlations between evolutionary measures and the performance of CVDP. The statistical results show that RNC, RDC, and RUC show no correlation with four performance indicators. ARMC shows weak or medium positive correlations with Recall and F‐measure. RLCC and RIC show very strong or strong negative correlations with Recall and F‐measure. The results indicate that the correlations between the proposed evolutionary measures and the performance of CVDP are different, which can guide the training set selection of CVDP.

Abstract Background Line‐level software defect prediction (LL‐SDP) serves as a valuable tool for developers to detect defective lines with minimal human effort. Recently, GLANCE was proposed as a readily implementable baseline for assessing the efficacy of newly proposed LL‐SDP models. Problem While DeepLineDP, a cutting‐edge LL‐SDP model rooted in deep learning, has demonstrated state‐of‐the‐art performance, it has not yet been compared against GLANCE. Objective We aim to empirically compare DeepLineDP with GLANCE to obtain a comprehensive understanding of how deep learning contributes to solving the LL‐SDP challenge. Method We compare GLANCE against DeepLineDP to assess the extent to which DeepLineDP surpasses GLANCE in predicting defective files and identifying problematic lines. In order to obtain a reliable conclusion, we use the same dataset and performance metrics utilized by DeepLineDP. Result Our experimental findings indicate that DeepLineDP does not outperform GLANCE in LL‐SDP. This suggests that the application of deep learning, in this context, does not yield the anticipated significant improvements. Conclusion This finding underscores the need for further research in deep learning‐based LL‐SDP to attain the state‐of‐the‐art performance that remains elusive for less advanced techniques.

With the progressive augmentation of the density of 3-D processor arrays, some processor elements (PEs) often fail due to overload or overheating during massively parallel computing operations. Therefore, it is necessary to take effective fault-tolerant technology to ensure the reliability of the system. This article investigates an efficient reconfiguration method to construct 3-D fault-free logical subarray with more fault-free PEs and less interconnection length (interlength). First, we propose a novel method based on the barrel effect to find the bottleneck plane of 3-D processor arrays. Second, an efficient compensation strategy is proposed to replace faulty PEs on adjacent physical planes with fault-free PEs on the bottleneck planes, which leads to more fault-free PEs that can be used to construct the subarray. Then, we propose a heuristic to construct the subarray and optimize iteration redundancy to accelerate reconstruction. Finally, a heuristic optimization algorithm is proposed to reduce the interlength between PEs, which can reduce the dynamic power consumption and communication costs. In addition, we propose a more accurate method to calculate the lower bound of the interlength to better evaluate the performance of the algorithm. Simulation experiments show that, compared to the state-of-the-arts, on$128\times 128\times 128$host array, the utilization rate of fault-free PEs can be improved up to 15.6% and the interlength redundancy can be reduced by 78.2% for random faults. On$64\times 64\times 64$host array, the average improvement of the two indicators under clustered faults can reach 93.2% and 69.3%. Moreover, for all cases considered, the proposed new lower bound and reconstruction time can be reduced by an average of 18.47% and 76.13%, respectively.

With the ever-increasing integration and parallel computing capabilities of 3D processor arrays, the occurrence of processor elements (PEs) failures caused by various factors has become more prevalent. Therefore, the implementation of a fault-tolerant mechanism that uses the remaining fault-free PEs to reconfigure sub-array becomes critical. In this paper, we study the problem of reconfiguring a 3D subarray with as many fault-free PEs as possible, which has been shown to be NP-complete in previous work. Although prior algorithms have been effective under low fault densities, they are severely limited when faced with high fault densities. To address this, we first define the bottleneck of the 3D processor array, proposed a novel method to identify the physical bottleneck plane that restricts the reconfigurable size of the logical sub-array and prove its correctness. Then, we propose an effective compensation strategy that can fully utilize the fault-free PEs in the bottleneck plane. Under this strategy, a sliding-window weight calculation method is proposed to determine the priority of compensation. Finally, we proposed a heuristic algorithm, which can construct the maximum target array from different dimensions in polynomial time. Experimental results demonstrate that the proposed algorithm exhibits favorable performance in terms of harvest and degradation. For the random-failure model, the improvement in the harvest for fault-free PEs is up to 32.03% on a$32 \times 32 \times 32$host array with a 20% fault density. And for the clustered fault model, the improvement in harvest is up to 70.63% on a$32 \times 32 \times 32$host array distributed with 12 cluster failures of size$6 \times 6 \times 6$.

In [1, p. 4967], a figure citation is incorrect and “Fig. 3(c)” should be “Fig. 1(c)” in the left column, the fourth line from the bottom. It is corrected below.

Code coverage has been widely used as the basis for various software quality assurance techniques. Therefore, it is of great importance to ensure that coverage profilers provide reliable code coverage. However, it is challenging to validate the correctness of the code coverage generated due to the lack of an effective oracle. In this paper, we propose an effective approach based on control flow constraint solving to test coverage profilers and have implemented a coverage bug hunting tool, DOG (finD cOverage buGs). Our core idea is to leverage inherent control flow features to generate control flow constraints that the resulting coverage statistics should respect. If DOG identifies any unsatisfiable constraints, it signifies the presence of incorrect coverage statistics. In such cases, DOG provides detailed diagnostic information about the suspicious coverage statistics for manual inspection. Compared with the state-of-the-art works, DOG has the following prominent advantages: (1) wide applicability: DOG eliminates the need for multiple coverage profilers (as required by differential testing) and program variants (as needed in metamorphic testing), making it highly versatile; (2) unique testing capability: DOG effectively analyzes and utilizes relationships among available coverage statistics, boosting its testing capabilities; and (3) enhanced interpretability: DOG provides clear control flow explanations for incorrect code coverage, enabling the localization of suspicious coverage areas. During our testing period with DOG, we successfully identified and reported 27 bugs in Gcov and llvm-cov, both widely-used coverage profilers. Of these, 17 bugs have been confirmed (11 have been fixed), 3 were deemed expected behaviors by developers, and 7 remain unresolved. Remarkably, 21 out of 24 unexpected bugs had been latent for over two and a half years, and nearly half of the coverage bugs (10 out of 24) were undetectable by state-of-the-art coverage profiler validators. These results demonstrate the effectiveness and importance of using DOG to improve the reliability of code coverage profilers.

Cross-version defect prediction (CVDP) has attracted more attention of researchers in recent years. For an evolutionary project, multiple versions will be produced during the process of software evolution. However, for multiple versions of an object-oriented project, the evolution degree (e.g. class change degree) between neighboring versions could affect the performance of CVDP. Therefore, how to measure the evolution degree of neighboring versions and explore the impact on the performance of CVDP are very important. Based on the neighboring versions of evolutionary projects, this paper proposed six evolutionary measures from three aspects of class change, metric change, and label change, including ratio of new classes (RNC), ratio of deleted classes (RDC), average ratio of metric change (ARMC), ratio of label changed classes (RLCC), ratio of unchanged classes (RUC), and ratio of interference classes (RIC). Spearman's rank correlation coefficient was applied to show the correlations between evolutionary measures and the performance of CVDP. An empirical study was conducted on 40 versions of 11 projects from the PROMISE repository. The performance of CVDP was evaluated with F-measure and AUC. The statistical results show that RNC, RDC, and RUC show no correlation with F-measure and AUC. ARMC shows a medium positive correlation with F-measure. RLCC and RIC show very strong or strong negative correlations with F-measure. The results indicate that the correlations between the proposed evolutionary measures and the performance of CVDP are different, which can guide the training set selection of CVDP.

In recent years, many intelligent optimization algorithms have been applied to the class integration and test order (CITO) problem. These algorithms also have been proved to be able to efficiently solve the problem. Here, the design of fitness function is a key task to generate the optimal solution. To better solve the class integration and test order problem, we propose a new fitness function to generate the optimal solution that achieves a balanced compromise between the different measures (objectives) such as the total number of stubs and the total stubbing complexity in this paper. We used some programs to compare and evaluate the different approaches. The experimental results show that our proposed approach is encouraging to some extent in solving the class integration and test order problem.

Sensors in wireless sensor network (WSN) are usually deployed in the wild or even hostile circumstance. What is worse, most of the sensors have limited communication bandwidth, computation resources and energy. Therefore, it is challenging to ensure the security of WSN without decreasing its network performance. Network coding (NC) is a promising way for improving communication capability in WSN, e.g., high throughput, robustness and low-energy. Nevertheless, network coding is vulnerable to malicious attacks. Presently, many secure detections, such as information theoretic-based or cryptographic-based techniques, have been proposed to deal with a single type of attack, but are incapable of resisting the joint attacks, e.g., the union of pollution attacks and replay attacks. In this paper, a secure detection service is presented. It is deployed on every node of WSN to monitor, manage and control the messages passing through them in real-time. In the service, a lightweight timestamp-based message authentication code, namely TMAC, is designed with Exclusive OR network coding. Based on TMAC and time synchronization technique, a joint detection is implemented to resist pollution attacks and replay attacks synchronously. The correctness of the detection service is proved. Finally, the performance evaluation shows that the detection scheme brings negligible extra-expense in communication bandwidth and computational complexity compared to MAC-based schemes, and consumes energy lowly compared to other joint detection schemes.

Metric transition systems (MTSs) are proposed for quantitative verification of reactive systems. There are already a number of papers on quantitatively analyzing behaviors of systems based on MTSs. In this article, we make further progress along this research line by lifting safety properties, which assert that nothing “bad” happens during execution of systems, to MTSs. First, we introduce a distance threshold$\alpha \ \text{taken from [0,1],}$which is used to analyze to what extent a system satisfies its specification. Then, we present a quantitative extension of safety properties, called$\alpha$-safety properties. Furthermore, we give an alternative characterization of$\alpha$-safety properties by means of their closure. In addition, an algorithm for verifying whether a system satisfies a subclass of$\alpha$-safety properties is developed, assuming that the method to convert a regular$\alpha$-safety property to an equivalent metric finite automaton has been given. Finally, we present an example to illustrate our approaches.

Refinement relations, such as trace containment, simulation preorder, and their alternating versions, have been successfully applied in formal verification of concurrent systems. Recently, trace containment and simulation preorder have been adopted and developed in fuzzy systems, but the generalization of their alternating versions to fuzzy systems has not been investigated. To satisfy the need for modeling and analyzing fuzzy systems, this article proposes two types of refinement relations called fuzzy alternating trace containment and fuzzy alternating simulation preorder, based on fuzzy concurrent game structures (FCGSs) under the Gödel semantics. These two fuzzy notions inherit properties from the corresponding classical setting. For example, fuzzy alternating simulation preorder for finite-state FCGSs can be computed in polynomial time; fuzzy alternating simulation preorder is a fuzzy subset of fuzzy alternating trace containment, and both relations can be logically characterized in terms of fuzzy version of alternating-time temporal logic. These properties make the theory developed here suitable for the modeling and verification of fuzzy systems.

We present Reflector, to support both high-level and low-level I/O monitoring through user-defined interfaces such as HDF5 and NetCDF in addition to POSIX- and MPI-IO. We evaluate Reflector on both an on-premises 500-core HPC cluster and a leadership-class supercomputer at the Lawrence Berkeley National Laboratory. Preliminary results are promising as the system prototype incurs negligible performance overhead and clearly illustrates the I/O patterns and bottlenecks of multiple applications.

Software evolution is an important activity in the life cycle of a modern software system. In the process of software evolution, the repair of historical defects and the increasing demands may introduce new defects. Therefore, evolution‐oriented defect prediction has attracted much attention of researchers in recent years. At present, some researchers have proposed the process metrics to describe the characteristics of software evolution. However, compared with the traditional software defect prediction methods, the research on evolution‐oriented defect prediction is still inadequate. Based on the evolution data of object‐oriented programs, this study presented two new process metrics from the defect rates of historical packages and the change degree of classes. To show the effectiveness of the proposed process metrics, the authors made comparisons with the code metrics and other process metrics. An empirical study was conducted on 33 versions of nine open‐source projects. The results showed that adding the proposed process metrics could improve the performance of evolution‐oriented defect prediction effectively.

In this paper, we investigated the technique for improving the reliability of 3-D processor with faults by reconfiguring a 3-D fault-free subarray utilizing as many nonfaulty process elements (PEs) as possible. A novel flexible rerouting scheme is proposed, which makes the PEs can be rerouted or bypassed in three dimensions, hence increasing the number of neighbors of each element to construct a logical array. Under this scheme, an efficient heuristic algorithm is presented to construct a logical array. The experimental results show that the proposed algorithm under flexible rerouting scheme can produce logical arrays with higher harvest from the host arrays with faults for the random fault scenarios, the improvement is by up to 46.47% compared to the state-of-the-arts.

Software defect prediction (SDP) is an available way to enhance test efficiency and guarantee software reliability. However, there are more clean instances than defective instances in real software projects, and this results in severe class distribution skews and gets the poor performance of classifiers. So solving the class-imbalance problem in SDP has attracted growing attention from industry and academia in software engineering. In this paper, we propose a novel class-imbalance learning approach for both within-project and cross-project class-imbalance problem. We utilize the thought of stratification embedded in nearest neighbor (STr-NN) to produce evolving training datasets with balanced data. For within-project, we directly employ the STr-NN approach for defect prediction. For cross-project, we first introduce transfer component analysis to mitigate the distribution differences between source and target dataset, and then employ the STr-NN approach on the transferred data. We conduct experiments on PROMISE and NASA datasets using ensemble learning based on weight vote. Experimental results indicate that our approach has higher area under curve (AUC), Recall and comparable probability of a false alarm (pf), and F-measure than some existing methods for the class-imbalance problem.

The computational study on finite/infinite-state systems, probabilistic systems, and finite-state fuzzy systems, has received much attention recently. In contrast, there are very few results for algorithmic analysis of infinite-state fuzzy systems. In this paper, we introduce fuzzy pushdown termination games (FPDTGs), which are an extension of fuzzy pushdown automata with a game feature and can serve as a formal model of infinite-state fuzzy systems. We investigate some computational issues of the games under termination objectives for two players: the goal of player-1 is to maximize the truth value of eventually terminating at some given configurations with the empty stack, while player-2 aims at the opposite. Some interesting results are obtained. For example, we show that both players have optimal memoryless strategies and the same value. The problem of computing the value can be solved in exponential time when the triangular norm is chosen as the minimum one. Furthermore, we present efficient algorithms for computing the values of two special subclasses of FPDTGs. The potential for practical use of our model is demonstrated by a case study on a manufacturing system.

Network coding has become a promising approach to improve the communication capability for WSN, which is vulnerable to malicious attacks. There are some solutions, including cryptographic and information-theory schemes, just can thwart data pollution attacks but are not able to detect replay attacks. In the paper, we present a lightweight timestamp-based message authentication code method, called as TMAC. Based on TMAC and the time synchronization technique, the proposed detection scheme can not only resist pollution attacks but also defend replay attacks simultaneously. Finally

Software testing consumes a significant portion of software effort. Program entities such as branch or definition–use pairs (DUPs) are used in diverse software development tasks. In this study, the authors present a novel evolution‐based approach to generating test data for all definition–use coverage. First, the subset of DUPs, which can ensure the coverage adequacy, is computed by a reduction algorithm for the whole DUPs. Then they apply a genetic algorithm to generate test data for the subset of DUPs. Furthermore, the fitness of an individual depends on the matching degree between the traversed path and the definition‐clear path of each target DUP. They also investigate the coverage and the size of test cases of test data generation by applying the authors’ approach on 15 widely used subject programs. The experimental results show that their approach can reduce the size of test cases that generated without affecting the coverage rate.

Internet of Things (IoT) can provide new value-added service by connecting the physical devices to virtual environments association with their context, and there is also a huge demand in ad hoc services by the end users for IoT applications. By extending mashup concept into IoT applications, we can achieve a novel and more lightweight services creation approach. This paper proposes a lightweight IoT service mashup middleware based on REST-style architecture for IoT applications, and design an uniform sensor devices access and dynamically protocol stack management framework, propose a distributed publish/subscribe based messages distribution service, and situational IoT services mashup approach, which can be integrated easily to create new composite and situational applications, and also apply the REST principles to define an extensible interface to build comprehensive and situational mashup applications. Based on proposed service mashup middleware, the end user can integrate applications and services in a more lightweight manner. We also illustrated the scenarios for RESTful Web service mashups representing for coal mine safety monitoring and control automation. In the experiments, the end-user evaluation has been conducted to evaluate the middleware, and also the performance has been measured and analyzed.

Background. Recent years have seen an increasing interest in cross-project defect prediction (CPDP), which aims to apply defect prediction models built on source projects to a target project. Currently, a variety of (complex) CPDP models have been proposed with a promising prediction performance. Problem. Most, if not all, of the existing CPDP models are not compared against those simple module size models that are easy to implement and have shown a good performance in defect prediction in the literature. Objective. We aim to investigate how far we have really progressed in the journey by comparing the performance in defect prediction between the existing CPDP models and simple module size models. Method. We first use module size in the target project to build two simple defect prediction models, ManualDown and ManualUp, which do not require any training data from source projects. ManualDown considers a larger module as more defect-prone, while ManualUp considers a smaller module as more defect-prone. Then, we take the following measures to ensure a fair comparison on the performance in defect prediction between the existing CPDP models and the simple module size models: using the same publicly available data sets, using the same performance indicators, and using the prediction performance reported in the original cross-project defect prediction studies. Result. The simple module size models have a prediction performance comparable or even superior to most of the existing CPDP models in the literature, including many newly proposed models. Conclusion. The results caution us that, if the prediction performance is the goal, the real progress in CPDP is not being achieved as it might have been envisaged. We hence recommend that future studies should include ManualDown/ManualUp as the baseline models for comparison when developing new CPDP models to predict defects in a complete target project.

Anomaly detection as a kind of intrusion detection is good at detecting the unknown attacks or new attacks, and it has attracted much attention during recent years. In this paper, a new hierarchy anomaly intrusion detection model that combines the fuzzy c-means (FCM) based on genetic algorithm and SVM is proposed. During the process of detecting intrusion, the membership function and the fuzzy interval are applied to it, and the process is extended to soft classification from the previous hard classification. Then a fuzzy error correction sub interval is introduced, so when the detection result of a data instance belongs to this range, the data will be re-detected in order to improve the effectiveness of intrusion detection. Experimental results show that the proposed model can effectively detect the vast majority of network attack types, which provides a feasible solution for solving the problems of false alarm rate and detection rate in anomaly intrusion detection model. Copyright © 2016 John Wiley & Sons, Ltd.

A two-dimensional mesh-connected processor array is an extensively investigated architecture used in parallel processing. Massive studies have addressed the use of reconfiguration algorithms for the processor arrays with faults. However, the subarray generated by previous algorithms contains a large number of long interconnects, which in turn leads to more communication costs, capacitance and dynamic power dissipation. In this paper, we propose novel techniques, making use of the idea of network flow, to construct the high-performance subarray, which has the minimum number of long interconnects. First, we construct a network flow model according to the host array under a specific constraint. Second, we show that the reconfiguration problem of high-performance subarray can be optimally solved in polynomial time by using efficient minimum-cost flow algorithms. Finally, we prove that the geometric properties of the resulted subarray meet the system requirements. Simulations based on several random and clustered fault scenarios clearly reveal the advantage of the proposed technique for reducing the number of long interconnects. It is shown that, for a host array of size 512 × 512, the number of long interconnects in the subarray can be reduced by up to 70.05 percent for clustered faults and by up to 55.28 percent for random faults with density of 1 percent as compared to the-state-of-the-art.

With the development of web service, more and more attention has been drawn to web service in recent years. However, the damage caused by service security problems is becoming more and more serious nowadays. This paper develops a web service security analysis tool, WSSecTool, which is based on program slicing. This tool includes three modules namely slicing module, safety publishing module and testing module. Slicing module analyzes source codes of web service to generate method dependence graph (MDG). After MDG is generated, the tool slices MDG to detect the unsafe methods and the spread of them. Safety publishing module helps to hide unsafe methods to make them invisible to outer users after publishing. Testing module can test the services published by this tool to validate the correctness and feasibility of our analysis method. The experiments show that our tool is effective and practical.

Considering the execution path and cut operators of a Prolog program can improve the precision of program analysis. Known semantics for Prolog either makes use of limited amount of path information and hence leads to less precise analysis or is goal dependent and therefore not suitable for goal independent program analysis. This paper deals with the problems by proposing a goal-independent denotational semantics for Prolog with cut, from which we can compute the set of partially computed answers associated to each program point that are obtained in the execution of any goal. With existing abstraction techniques this semantics can be abstracted into a finitely computable semantics that can serve as a basis for goal-independent Prolog program analysis.