A variable instruction set processor provides a dictionary that enables the compiler to configure the best instruction set to use for executing the program being compiled. This paper describes Cognigine's variable instruction set communication architecture (VISC Architecture) and the implementation of a compiler that provides effective compilation and optimization support for this target. The compiler implementation involves the use of an abstract operation representation that enables the code generator to optimize toward the core architecture of the processor without committing to any specific instruction format. It then uses an enumeration approach to instruction scheduling that determines the final forms of the instructions to be generated while still adhering to the irregular constraints imposed by the architecture. The enumeration approach also allows the incorporation of dictionary reuse functionality to provide trade offs between program performance and dictionary budget. Finally, we provide experimental results to show the effectiveness of these compilation techniques in supporting Cognigine's VISC Architecture.

This paper proposes a precise approach to register allocation for irregular-register architectures which is based on 0-1 integer programming (IP). Prior work shows that IP register allocation is feasible for RISC architectures, which have uniform registers and register usage. Extensions to the prior work are proposed that precisely model register irregularities including combined source/destination specifiers, memory operands, and variations in the cost of register usage. The x86 architecture is selected as a representative irregular-register architecture for experimental study. An IP register allocator is built for the x86 architecture within the Gnu C Compiler (GCC), and is compared experimentally with GCC's graph-coloring register allocator. Experimental results show that the IP allocator reduces register allocation overhead by 61% compared with the graph coloring allocator. The results also show that the x86 IP allocator is dramatically faster than the prior RISC IP allocator; because of the smaller number of registers in the x86 architecture and because of the register irregularities. These results suggest that IP register allocation is well suited for irregular-register architectures.

A new approach allows low-cost concurrent detection of two important types of faults, software and hardware data-access faults, using an extension of the existing signature monitoring approach. The proposed approach detects data-access faults using a new type of redundant data structure that contains an embedded signature. Low-cast fault detection is achieved using simple architecture support and compiler support that exploit natural redundancies in the data structures, in the instruction set architecture, and in the data-access mechanism. The software data-access faults that the approach can detect include faults that have been shown to cause a high percentage of system failures. Hardware data-access faults that occur in all levels of the data-memory hierarchy are also detectable, including faults in the register file, the data cache, the data-cache TLB, the memory address and data buses, etc. Benchmark results for the MIPS R300D processor executing code scheduled by a modified GNU C Compiler show that the new approach can concurrently check a high percentage of data accesses, while causing little performance overhead and little memory overhead.