The architecture design phase is one of the most important steps in the system LSI development process. In this paper, we propose a C-based pipeline architecture design methodology and apply it to the design of the output probability computation circuit for a real time speech recognition system. Several variable length vector pipeline architectures accelerated by loop optimization, memory access optimizations, and application-specific circuit design were implemented to calculate the hidden Markov model (HMM) output probability at high speed and their performances evaluated.

Speech recognition is becoming a popular technology for the implementation of human interfaces. However, conventional approaches to large vocabulary continuous speech recognition require a high performance CPU. In this paper, we describe a speech-recognition system designed using a C-based design methodology and compare three hardware implementations for the computationally intensive parts. Pipelining, parallel processing and cache memory solutions to compute the hidden Markov model (HMM) output probability at high speed were implemented and their performances evaluated. It is shown that designers can rapidly explore a wide range of complex circuits in a using this methodology and that real time speech recognition in small portable systems is possible.

In system LSI design, a desirable system is one that allows the designer to describe, partition, and verify systems, and to generate circuits efficiently. In this paper, we describe a C-based system LSI design system called Bach which we have developed. Using the example of an MEPG-4 video codec design, we summarize its design flow, effects and current issues.

Abstract In this paper, we propose a cell synthesis method for a Salicide process. Our method utilizes the local interconnect between adjacent transistors, which is available in some Salicide processes, and optimizes the transistor placement of a cell considering both area and the number of local interconnects. In this way we reduce the number of metal wires and contacts. The circuit model is not restricted to conventional series-parallel CMOS logic, and our method enables us to synthesize CMOS pass-transistor circuits. Experimental results show that our method uses the local interconnect effectively, and optimizes both cell area and metal wire length. I.

This paper presents a method for thread partitioning for a hardware compiler Bach.Bach synthesizes RT level circuits from a system description written in Bach-C language, where a system is modeled as communicating processes running in parallel.The system description is decomposed into threads, i.e., strings of sequential processes, and then converted into synthesizable behavioral VHDL models.The proposed method attempts to find a partitioning of a given system description into threads that maximize resource sharing among processes in the threads.Experiments on two real designs show that the circuit sizes were reduced by 3.7% and 14.7%.We also show the detailed statistics and analysis of the size of the resulting gate level circuits.

In this paper, we propose a scheduling method for synchronous communication between threads in the Bach hardware compiler. In this method, all communications are extracted from a behavioral Bach-C description and statically prescheduled to synchronize communications between threads if possible. Then all the operations and communications of each thread are synthesized independently according to the prescheduling result. Consequently, we can synthesize large system LSIs efficiently, because we do not need to synthesize the whole system descriptions at once to synchronize communications. Experimental results show that our method improves throughput of synthesized circuits and is applicable to large systems designed with the Bach hardware compiler.

This paper presents new binding and scheduling algorithms for a retargetable compiler which can deal with diverse architectures. Application specific embedded processors often includes a "nonorthogonal" datapath where all the registers are not equally accessible from all the functional units. Nonorthogonal datapath makes a binding task very hard because inadvertent assignment of an operation to a functional unit may rule out all the possible assignments to other operations due to reachability constraints among datapath resources. Scheduling must take register capacity constraints into account in addition to resource constraints. We discuss these problems and propose algorithms to solve them.

A layout approach is described dedicatedly for MMICs, in which layout elements are transistors, inductors, capacitors, resistors, coplanar-waveguides, etc., implemented by GaAs fabrication process. The layout issue typical of such MMICs consists essentially in how to realize a single-layered placement of different shapes of layout elements under a variety of spacing and orientating constraints as well as shaping variations. In this paper, the interconnection requirements among the elements are represented by a graph, to which a planarization algorithm is effectively applied. On the basis of the planarization result, the physical placement is first constructed with the use of a merging scheme and then refined iteratively by means of a new rectangle-packing algorithm. Experimental results are also shown to demonstrate the practicability of the described layout approach.

A layout approach for monolithic microwave integrated circuits (MMICs) is described, in which layout elements are transistors, inductors, capacitors, resistors, coplanar waveguides, etc., implemented in a GaAs fabrication process. The layout issue typical of such MMIC's consists essentially in how to realize a single-layered placement of different shapes of layout elements under a variety of spacing and orienting constraints as well as shape variations. In this paper, the interconnection requirements among the elements are represented by a graph, to which a planarization algorithm is applied. On the basis of the planarization result, the physical placement is first constructed with the use of a merging scheme and then refined iteratively by means of a new rectangle-packing algorithm. Experimental results are also shown to demonstrate the practicability of the described layout approach.

This paper presents a novel way of evaluating architecture of embedded custom DSPs which helps designers optimizing the datapath configuration and the instruction set. Given a datapath structure, it evaluates the performance in terms of an estimated number of steps to execute the target program on the datapath. A concept of "parallel constraint" is newly introduced, which enables evaluation of the impact of instruction format design on the performance without explicitly specifying the instruction format. The number of execution steps is estimated by a combination of static analysis and dynamic analysis. It enables fast and precise estimation of actual performance in the early design stage. We show some experimental results on an actual signal processor to demonstrate the accuracy of estimation and the usefulness of this method in architecture design.

This paper proposes a novel method to estimate and to re-duce redundant power of synchronous circuits at RT level design. Because much redundant power is caused by redun-dant clockings which activate registers unnecessarily, we de-tect these clockings. They are detected from the difference of the numbers of incoming and outgoing data of a regis-ter. And then we introduce gated-clock scheme to reduce the power consumption of the circuits using our estimation re-sults. Experimental results demonstrate the accuracy of our method and the effect on power reduction. 1

In this paper, a new method for the design of complex multimedia ASIC is introduced.Using this design method, VLSI with embedded software and high-speed emulators can be developed concurrently.The method has proven to be eective through actual design of VLSI for audio compression and decompression in a Mini-Disc system.

In this paper, we propose a hybrid floorplanning methodology. Two hierarchical strategies for avoiding local optima during iterative improvement are proposed: (1) Partial Clustering, and (2) Module Restructuring. These strategies work for localizing nets connecting small modules in small regions, and conceal such small modules and their nets during the iterative improvement phase. This method is successful in reducing both area and wire length in addition to reducing the computational time required for optimization. Although our method only searches slicing floorplans, the results are superior to the results obtained even with non-slicing floorplans. We applied our method to the largest MCNC floorplan benchmark example, ami49, and industrial data. For the ami49 benchmark, we obtained results superior to any published results for both estimated area and routing results.

No abstract available.