In addition to full scan design, design-fortestability (DFT) methods at register transfer level have been proposed to reduce the number of test patterns for VLSI. As one of the conventional DFT methods, a controller augmentation method was proposed that control signals on the state transitions of invalid states in controllers which cannot be transitioned during functional operation were designed to perform concurrent testing for hardware elements in data-paths. As the result, the number of test patterns was reduced by 33.47% on average compared to original circuits. However, the area overhead was 7.12% on average. In this paper, we propose a don’t care filling method for control signals on state transitions of valid states that minimizes the estimated number of test patterns for data-paths. Experimental results show that the estimated number of test patterns was reduced by 32.64% with 1.37% area overhead on average compared to original circuits.

Classification of wafer map defect patterns is important to monitor occurrence and further to assist root cause analysis of manufacturing-process-induced systematic defects. CapsNet, a variant of convolutional neural network, contains a decoder network which tries to reconstruct an input image, and during training loss function is calculated not only for prediction error but also for difference between reconstructed and input images. Improving the quality of reconstructed image might lead to improvements on prediction capability. It would also assist root-cause analysis of systematic defects, since not only category but also locations and shapes for the predicted systematic defect are more clearly reported. In this paper we report on our improvements on reconstruction capability of CapsNet-based wafer map defect pattern classifier. Mainly targeting scratch defect pattern, we tuned network architecture of the classifier. We generated a synthesized high-resolution wafer map dataset, and applied a mixture of sub-categories as training data in order to improve reconstruction capability even under appearances of noises on a wafer and chopped curves. We also propose a set of measures to evaluate quality of a reconstructed defect pattern images.

With the exponential growth of facial authentications, the face anti-spoofing area has come to play an indispensable role as a shield, protecting those systems against facial impostures. However, because most current anti-spoofing technologies work with type-specific supervision, they are only effective in their respective spoof types, which means they are unlikely to prove robust for unidentified attack forms that are beyond their predefined supervised limitations. With this point in mind, we herein propose a novel Adversarial Distribution Generative Network (ADGN) that extends its spatial attention to a comprehensive global context, thus extensively raising the level of generality for unknown cases that inherently provide few or even no clues with which to learn. In this paper, we are more in favor of speculating on 3D mask attacks, where a great scarcity of prior knowledge is virtually inevitable due to their prohibitive costs. We also demonstrate the resilience of our proposed model and test it against publicly available datasets on both seen and unseen spoof scenarios. This intends to show how our model provides competitive detecting performance against a wide range of spoof types in comparison with previous state-of-the-art methods.

Classification of wafer map defect patterns is important to monitor occurrence and further to assist root cause analysis of manufacturing-process-induced systematic defects. In this study we develop CapsNet-based wafer map defect pattern classifier. CapsNet is a variant of convolutional neural network, which extract features of images as vectors, not as scalars, and is expected to extract features more accurately under fluctuations of locations, angles, and scales of features in input images. Experimental results indicate that, by combining 2-stage (detector and classifier) approach, the proposed scheme shows higher accuracy on WM-811K real wafer map dataset for 8 categories in comparison to the previous work, on average and especially on the categories “Donut” and “Scratch,” which are difficult to accurately categorize by the previous work.

High power dissipation can occur by high launch-induced switching activity when the response to a test vector is captured by flip-flops (FFs) in transition delay fault scan testing, resulting in excessive IR drop. Since excessive IR-drop significantly increases path delay, and thus might result in timing errors, such testing induces unnecessary yield loss in the deep submicron era. It is known that test manipulation methods using X-identification and X-filling are effective to reduce power dissipation in the capture cycle. Conventionally, these two techniques have been independently studied for a capture power dissipation problem. However, their effects depend on the application results of each other. In this paper, we propose an X-identification-filling method to co-optimize capture power dissipation using a Partial MaxSAT Solver. The method justifies values assigned to propagate target faults to pseudo primary outputs and reduces the number of transitions on as many internal signal lines as possible. Experimental results show that our proposed method reduced the numbers of capture-unsafe test vectors and unsafe faults compared with conventional methods.

In Software-Defined Networking (SDN) it is important to efficiently partition the rule table into sub-tables and distribute them to the switches over the network in order to reduce storage size of each switch. In this paper we propose a fine-grained rule table partitioning, where the original rule table is partitioned into n sub-tables and every switch has k sub-tables. We formulate the problem as a satisfiability (SAT) problem, and use SAT solver to obtain an optimal sub-table allocation that minimize the storage size under a given k. Results indicate that the proposed scheme with k = 2 can reduce the storage size required to switches in comparison to the conventional scheme, that corresponds to k = 1.

Non-scan based test generation is required to reduce test cost and improve security. However, sequential test generation consumes a lot of time to identify untestable faults. Therefore, it is important to identify untestable faults in the preprocessing of the test generation. In this paper, an unreachable state identification method, which identifies whether states on a few flip-flops can be justified using SAT, and an untestable fault identification method using the unreachable states are proposed. Experimental results show that our proposed method was effective compared with conventional methods.

In Software-Defined Networking (SDN) it is important to efficiently partition the rule table into sub-tables and distribute them to the multiple switches over the network. In this paper we proposed an optimal rule table distribution strategy by applying satisfiability (SAT)-based approach. N-coloring problem for partitioning is formulated as conjunctive normal form (CNF), and by repeatedly running SAT solver we can obtain maximum number of partitions.

Advances in semiconductor device manufacturing technology, which have enabled reduced feature size and higher integration, have resulted in a gap between the defect level estimated at the design stage and that reported for fabricated devices. As one possible strategy to control test quality and cost, the authors have proposed weighted fault coverage estimation. In this study, we propose layout-aware, fast and compact test pattern set generation considering both bridge and open weighted fault coverages. The proposed scheme applies two-step test pattern generation where only second pattern set is reordered with fixed size of search window, achieving O(n) computational complexity. Compared to simple greedy-based reordering, the experimental results indicate that the proposed scheme with a 10% initial target fault size and a fixed small window size achieves approximately 100 times runtime reduction with further in exchange for about 5% pattern count increment.

Delay (or disruption) tolerant networks (DTNs) have widely studied as promising technology for providing communications in environments where all nodes are not connected with each other. Assuming the existence of adversary nodes, in this study we evaluate effectiveness of erasure-code based DTN routing in terms of secure transmission. We combine secret-sharing-based multi-path routing with several routing strategies, and evaluate the ratio of successful transmission by simulation.

Ambipolar gate-controllable FETs and their application to tile-based regular design are expected to meet the demand for lower power consumption, higher integration, and reduction of design efforts. In this study, we propose spare-tilebased dependable Sea-of-Tiles architecture for ambipolar devices. We also introduce tile arrangement strategy considering logic function, aiming at reduction of MUXs and switches.

Advances in semiconductor device manufacturing technology, which have enabled reduced feature size and higher integration, have resulted in a gap between the defect level estimated at the design stage and that reported for fabricated devices. As one possible strategy to accurately estimate defect level, the authors have proposed weighted bridge fault coverage estimation. In this study, we establish unified weighted fault coverage, which takes both bridge and open faults into account, and we propose fast and compact test pattern set generation. The proposed scheme applies two-step test pattern generation where only second pattern set is reordered with search window for speed-up. Compared to simple greedy-based reordering, the experimental results indicate that the proposed scheme with a 10% initial target fault size and a 10% window size achieves approximately 10 times processing time reduction in exchange for a 10% pattern count increment.

In this paper, we propose a new low capture power test generation method based on fault simulation to reduce the number of unsafe faults. The method uses capture-safe test vectors in an initial test set to generate new test vectors. Our experimental results show that the use of this method reduces the number of unsafe faults by 94% on average, and while requiring less test generation time compared with the conventional low capture power test generation method.

In this study we discuss fault tolerant routing mechanism for the P2P network, Chord, considering the existence of faulty or malicious nodes. We propose a routing protocol which works despite existence of faulty nodes. We modify the original Chord routing protocol so that it can handle redundant lookups of multiple "knuckles," and replica or data fragments allocation on knuckles. Analysis based on mathematical models and simulations show that the proposed protocol effectively avoids the interruption of object supply caused by the target node fault and/or the acquisition failure of objects caused by malicious nodes tampering.

Recently, a microcomputer and a FPGA are apt to be used for control of the power conversion circuits because of their capability to simplify the parameter resetting and also their flexibility on the basis of programming by software. On the other hand, the control circuits are getting extremely close to the high current main circuit. Thus the electro-magnetic radiation generated nearby the high current pulse may affect the control circuit as transient faults. In this study, we focus on transient noise caused by switching activities of a DC-DC converter and propose a dependable digital power control circuit by FPGA. The basic idea is to keep the sampling times as far away from the switching times as possible to avoid the effects of transient noise. A control circuit, with the proposed method applied, is designed and its effectiveness is shown by simulations.

In recent electronic vehicles (EVs) and hybrid vehicles (HVs), there are growing concerns about electromagnetic interference (EMI) caused by significantly-high voltage switching in DC-DC converters. The most remarkable characteristic of the coverter noise is in its periodicity. In this article, a noise injection experiment to a controller area network (CAN) bus by using a DC-DC converter is presented. Dispite the switching period of the converter was much shorter than the time length of a data frame transmission, we found that the switching did not always cause CAN errors. On the basis of this observation, we discuss characteristics of the converter noise and some basic ideas for improving the immunity of CAN networks against the converter noise by using dependable computing techniques.

Shrinking feature size and higher integration on semiconductor device manufacturing technology bring a problem of the gap between the defect level estimated at the design stage from the reported one for fabricated devices. In this study, as one possible strategy to accurately estimate the defect level, we discuss on fault coverage estimation with more accuracy for the given test pattern set. We consider the probability that intermediate voltage caused by bridge/open defects is translated into logic values 0/1 at any of successive nodes. For each possible pair of signal lines in a given layout data, we execute critical area analysis. On the basis of critical areas obtained, we calculate weighted probabilistic bridge fault coverage, considering frequency of occurrence of each fault.

This paper releases a report of the application for the fault tolerant sequential circuit technique against periodical transient faults under highly electromagnetic environment. After implementing the proposed fault tolerant technique on a counter in our previous paper, as an example of how the proposed architecture performs on utility-scale sequential circuits, the result obtained by applying the technique to a processor is illustrated. On the basis of our logic simulation, we confirm that the originally designed 8-bit processor with functional BIST can avoid the periodical multiple transient faults. We further show that sequential circuits with a practical size of a processor can apply the fault tolerant technique with low overhead from the viewpoint of the circuit space.

In this paper we evaluate the effectiveness of cascaded triple modular redundancy (TMR) in terms of area-per-yield and defect level by applying to every stage of a pipelined processor. Considering a cascade of nine possible TMR stage architectures, we theoretically derive the area-per-yield on the basis of the given parameters of defect density and the number of stages. Also, assuming that a production test is independently applied for each module and voter in every stage and the pass/fail of a chip is determined on the basis of the test result, we theoretically derive the defect level for the given fault coverage. Numerical examples show that the application of cascaded TMR improves the area-per-yield and the defect level when manufacturing yield is low. In addition, some cases exist in which the number of stages minimize the area-per-yield or the defect level.

Some cloud storage services have recently introduced file versioning features by which more than one version of a file can be maintained. For providing file versioning with limited storage resources, it is essential to divide the resources among versions in accordance with the varied needs of numerous users. In this paper, we focus on applications in which newer versions of a file are more likely to be requested, which may be true in the case of many subscription services. We propose a new distributed data replication protocol supporting the file versioning feature. We also construct an analytical model that can derive an optimal allocation of the resources when the total number of replica nodes in a system and the distribution of the frequency of read requests for each version are given. In addition, we present some numerical examples obtained by simulations to show the good scalability and dependability of our system by assuming some realistic parameters.

We propose the fault model considering weak resistive opens inside the gate which might cause pattern-sequence-dependent and timing-dependent malfunction of the circuit. We assume the fixed observation interval for the signal transition, and derive the minimum resistance of intra-gate resistive opens to be detected as a fault by SPICE simulation. Based on the simulation results, we establish three fault models, that is, the one considering the location of the resistance, the one considering both the location and the resistance distribution, and the simplified one where str and stf faults considering the signal transition of the input ports are assumed. The coverage calculation for the primitive gates and small benchmark circuit reveals that the proposed models have more accuracy on the detection of weak open defects.

We are developing a system that automatically assesses Japanese technical reports submitted by university students. An important function of the system is to evaluate the accuracy of references in the reports. In this paper we propose a method to extract the sentences referenced in a report from the actual reference. The method extracts sentences using parse trees and word concepts from the reference. The experimental result shows that the fourth cumulative extraction rate of the method is about 90%.

We propose encoder-based comparator architecture to reduce hardware overhead of MBIST. Experimental results show the proposed architecture drastically reduce hardware overhead while maintaining the adaptability to the repair analysis.

Convolutional compactors offer a promising technique of compacting test responses. In this study the authors expand the architecture of convolutional compactor onto a Galois field in order to improve compaction ratio as well as reduce X-masking probability, namely, the probability that an error is masked by unknown values. While each scan chain is independently connected by EOR gates in the conventional arrangement, the proposed scheme treats q signals as an element over GF (2q), and the connections are configured on the same field. The authors show the arrangement of the proposed compactors and the equivalent expression over GF (2). The authors then evaluate the effectiveness of the proposed expansion in terms of X-masking probability by simulations with uniform distribution of X-values, as well as reduction of hardware overheads. Furthermore, the authors evaluate a multi-weight arrangement of the proposed compactors for non-uniform X distributions

We developed a learning system that supports in obtaining the capability of tracing source programs for novice programmers. The system has the following functions and characteristics: (1) It can display the source program and the flow chart of the program in parallel. (2) It can set similar problems based on basic program patterns semi-automatically. (3) It has a function to display the present and past contents of the variables. (4) We construct the system as a web-based server-client application.

The authors have developed a scheme for scan-based BIST that can compress test stimuli and responses by more than 100 times. The scheme is based on a scan-BIST architecture, and combines four techniques: the invert-and-shift operation, run-length compression, scan address partitioning, and LFSR pre-shifting. The scheme achieved a 100times compression rate in environments where Xs do not occur without reducing the fault coverage of the original ATPG vectors. Furthermore, the masking logic was enhanced to reduce data for X-masking so that test data is still compressed to 1/100 in a practical environment where Xs occur. The scheme was applied to five real VLSI chips, and the technique compressed the test data by 100times for scan-based BIST

Maintaining the replicated data between nodes can improve the dependability of data. We propose a probabilistic trapezoid protocol for replicated data that combines this protocol with the concept of a probabilistic quorum system. We analyzed read availability, the latest version read availability and the average number of nodes accessed for the protocol. Our numerical evaluations demonstrated that it improves not only read availability but also latest version read availability. Furthermore, when the number of nodes is greater than 100, it could effectively reduce system load. We designed and implemented a file transfer protocol to replicate data. Experimental results proved that the trapezoid protocol could achieve better throughput than quorum system or grid protocol. Despite node failure, the probabilistic trapezoid protocol also achieved relatively better throughput.

Convolutional compactors offer a promising technique of compacting test responses that include unknown values. One drawback of this compaction technique is error masking, i.e., some errors appearing in the test responses cannot be detected due to mutual cancellation. In this work, we theoretically analyze error-masking probability. First, we apply weight distributions of binary linear error-correcting codes to derive the error-masking probability. We then present a fast calculation scheme for 4- and 6-error-masking probabilities. Numerical examples reveal that they are about the same as those obtained by Monte-Carlo simulations. We also analyze X-masking probability, that is, the probability that an error is masked by unknown values. We present tree-search-based calculation, as well as approximated value

In this paper, we discuss the application of a seed-selection procedure for LFSR-based BIST to multiple scan chains, combined with a phase shifter. We introduced the procedures for selecting seeds and arrangement of phase shifters under the restriction of limiting additional hardware overheads, and evaluated them in respect to the number of test patterns required to achieve 100% fault coverage. Experimental results shows that that the test length was reduced in comparison with cases in which phase shifters or seed-selection procedures were not applied, under condition where the number of EOR gates in the phase shifter were restricted.

We have developed Souryu-I and II, connected crawler vehicles that travel in the rubble. They were developed for the purpose of finding survivors trapped in collapsed buildings. We have identified problems of these machines through experiments and studies, which are shape of the crawler, joint mechanism, dust- and waterproofing and communication system. We developed an improved model called Souryu-III based on these findings. It has unitized crawlers, new joint mechanism, dust proofing and waterproofing mechanism and tethered communication system with a new reel mechanism in order to address those problems. This paper describes Souryu-III, its mechanism and the experiments to test its mobile performance.

Replicating data is a promising way of improving the dependability of large distributed systems. The hybrid data replication protocol combines concepts of the tree quorum protocol and grid protocol. We present an analytical evaluation of read/write availability for the generalized hybrid data replication protocol, which extends the arrangement of nodes into a more general form to improve write availability. The average number of nodes accessed for read/write operations is also analyzed under the assumption that nodes might fail. Equations are derived based on node availability p, and numerical examples are shown. We use computer simulations to estimate the throughput for read/write operations.

We propose a technique of selecting seeds for the LFSR-based test pattern generators that are used in VLSI BISTs. By setting the computed seed as an initial value, target fault coverage, for example 100%, can be accomplished with minimum test length. We can also maximize fault coverage for a given test length. Our method can be used for both test-per-clock and test-per-scan BISTs. The procedure is based on vector representations over GF(2m), where m is the number of LFSR stages. The results indicate that test lengths derived through selected seeds are about sixty percent shorter than those derived by conventionally selected seeds for a given fault coverage. We also show that seeds obtained through this technique accomplish higher fault coverage than the conventional selection procedure. In terms of the c7552 benchmark, taking a test-per-scan architecture with a 20-bit LFSR as an example, the number of undetected faults can be decreased from 304 to 227 for 10,000 LFSR patterns using our proposed technique.

A scheme for testing SRAMs is proposed with a tester circuit consisting of SRAM-based reconfigurable cells. We first show an approach to reduce the number of reconfigurable cells required for the tester circuit. We then propose a tester for a 4 Mbit SRAM with reconfigurable cells of 16 bit data SRAMs. We also report the implementation of the proposed circuit. Four 16 bit reconfigurable cells, each of which consists of an SRAM and two CPLDs, were implemented, and mounted on a board. We confirmed that the tester functions correctly by performing a marching test.

The authors propose a method to extract the face area from a trainee's picture using mosaic templates and recognize a trainee's eye direction using separability filters in touch-type training using a camera. The recognition of a trainee's eye direction enable one to give a trainee warnings and appropriate advice, and these warnings and advice assist a trainee to learn touch-typing quickly. On the experimental results for twenty trainees' black-and-white pictures, the authors obtained an 83% recognition rate.

It is very important to develop technologies that automatically evaluate learners' answers for descriptive problems such as programming practice, in the e-learning environment. The case-based approach is one of the most promising technologies for automated evaluation. The key issue in implementing automated evaluation systems by the case-based approach is how one can acquire many evaluation cases and construct rich case-bases. This paper presents a solution to the issue, that is, a framework for sharing evaluation case-bases among instructors. Sharing case-bases promotes enrichment of the case-bases, because case-based evaluation systems obtain new cases through evaluation work, which is the collaboration between human instructors and computer systems. The framework for sharing case-bases is also expected to form the instructors' community and promote communication among instructors.

In this paper we evaluate the effectiveness of using convolutional codes under a time limit for recovery as a method for packet loss recovery. We analyze the method's operation when a limitation on the number of received packets is substituted for the time limitation, and derive the probability for a lost packet being recovered before the arrival of the limiting number of succeeding packets. We also evaluate this probability in the results of simulation and estimate the buffer size required for a decoder. Moreover we apply this method in constructing a dependable videoconference system and observe the resulting improvement in QoS.

The ability of convolutional-code-based FEC to recover from packet losses over a channel subjected to burst erasure is evaluated. We analyze the maximum lengths of a burst packet loss that can be recovered. We assume that only one burst packet loss has occurred, and consider the recovery conditions for given lengths, that is, numbers of lost packets. We also present conditions for the generator matrices, which are used to encode and decode convolutional-code-based redundant packets. We then apply a packet loss model based on a two-state Markov chain and use computer simulation to examine the ability of our approach to recover packets lost in transmission over bursty erasure channels. We show that this ability changes with the constraint length of the applied code and with the generator matrix, and find conditions for a matrix to have high levels of ability. Finally, we apply our method to the transfer of graphic data over the Internet, and use convolutional codes in the recovery process.

A new method to recover packet losses (n, n-1, m) convolutional codes is proposed. The method is used to encode and decode packets transmitted over the Internet. An independent erasure channel is assumed for packets transmission. We then theoretically analyze the method ability to recover packet losses. The sufficient conditions are derived for packet losses that can be recovered. We evaluate the method using computer simulations, supplemented by comparisons with a simple parity method, which has the same redundancy. The results show that the proposed method has a superior performance.

Packet losses due to congested traffic conditions in the Internet leads to the investigation of the reliable delivery of data to multicast receivers. In this paper, we examine the technique based on FEC, using (n, k, m) convolutional codes to recover lost packets. We show that when the redundant packets are generated by convolutional codes, a receiver can tolerate a certain amount of packet loss and still be able to obtain all data without requiring retransmission. We evaluate the effectiveness of the proposed approach to perform the recovery of lost packets for multicast transmission taking into account two different parameters: the number of packets needed to be sent to guarantee the reception of data, and the number of transmissions. Finally, we compare the proposed approach with the scheme when parity packets are based on Reed-Solomon codes. We demonstrate that the use of parity generated by convolutional coding is more efficient at reducing bandwidth requirements and the number of transmissions from the source.

We have measured the packet loss ratio, its time dependency, and the frequency of burst packet losses in Internet end-to-end communications. To do this, we developed a tool that sends and receives UDP (User Datagram Protocol) packets. Our measurements showed that long burst losses are more likely when the packet loss ratio is high. We then examined two models for calculating the burst packet loss, an independent loss model and a Markov-chain model, to see whether they explain the packet loss characteristics we measured. They did not, so we developed a sine model, in which the packet loss probability depends on the time of day. Theoretical analysis and simulations showed that this model explains the characteristics of the burst packet losses that we measured.