This paper introduces an ultra-low-power amplifier-less front-end architecture for amperometric electrochemical sensing. The proposed architecture can simultaneously regulate the potential difference between the required electrodes and perform current readout for an electrochemical sensor. A dual-side potentiostat regulation loop comprising dynamic latched comparators in conjunction with digital loop filters and current-steering DACs is proposed, with its detailed operation discussed in this paper. Implemented in a standard 180 nm CMOS process, this design achieves a current measurement range of 114.3 dB. It can operate over a wide range of sampling frequencies FS (100 Hz ~ 100 MHz) and supply voltages (1 V ~ 1.8 V). The whole interface IC consumes only 3.50 nA current at 1.2 V supply at a clock frequency of 1-kHz.

As the demand for embedding edge intelligence in vision systems continues to grow, future image sensors must become smarter and capable of performing efficient on-chip computation. This paper presents a hardware-friendly computational CMOS image sensor (C2IS) that performs signed analog-domain multi-bit convolution directly within the pixel array to enable energy-efficient embedded vision. The proposed C2IS uses a compact two-transistor (2T) pixel—without in-pixel weight memory or capacitors—while maintaining a 43% fill factor. By leveraging programmable column link switches and shared CTIA+SS-ADC channels, the system supports up to eight programmable convolution kernels per frame without requiring intermediate SRAM or DAC for partial-sum storage. Fabricated in a standard 0.18$\mu $m CMOS process, the prototype achieves 1.5-2.0 TOPS/W performance (normalized to 1-bit), corresponding to 14–112 fps at 61.8–82.4$\mu $W total chip power. A vision system incorporating the proposed C2IS demonstrates validation accuracy of 96.7% for handwritten digit recognition and 94.2% for hand gesture recognition. These results confirm the feasibility of this approach for low-power, high-density feature extraction, making it well suited for next-generation edge AI applications.

This paper presents a single-chip CMOS-MEMS flow sensing system for high-precision bidirectional gas flow detection, featuring a pulse-excited constant temperature difference (CTD) control scheme and a low-noise analog front-end using capacitively coupled chopper instrumentation amplifier (CCIA). The MEMS sensing structure is fabricated using a cost-effective surface micromachining process and thinned to$1.38~\mu $m, significantly enhancing system sensitivity and thermal efficiency. Two sensor prototypes, with MEMS opening sizes of$130~\mu $m and$170~\mu $m (named as Sensor 130 and Sensor 170), achieve record-high sensitivities of 24.74 mV/(m/s) and 30.84 mV/(m/s), respectively, within a linear flow range of ±5 m/s. Leveraging pulse excitation, the system dramatically reduces heating power down to 1.63 mW (Sensor 130) and 1.85 mW (Sensor 170). The CCIA readout circuit exhibits an ultra-low input-referred noise density of 5.86nV/$\surd $Hz, with a 1/$f$noise corner below 0.1 Hz, greatly improving low-flow detection capabilities of the sensor system. As a result, the overall system output noise density is measured at$1.93~\mu $V/$\surd $Hz, enabling minimum detectable flow velocities (MDFV) of 0.51 mm/s (Sensor 130) and 0.41 mm/s (Sensor 170). With its compact design, low power, and exceptional circuit performance, this cost-effective CMOS-MEMS flow sensing system is well-suited for high-precision flow measurement in industrial and IoT applications.

This paper presents a technique to effectively reduce the number of conversion cycles of the 1st-order incremental delta-sigma data converter (IADC1). Typically, an IADC1 requires 2Ncycles to achieve N-bit resolution if using a sinc1filter for reconstruction. The proposed quantization-skip technique can effectively reduce the average conversion cycles and, therefore, the energy consumption of an IADC1. Specifically, during conversion, the quantizer output is predicted using the previous bitstream pattern to achieve automatic bitstream fill-in without analog domain operations. Behavioral level simulations show that this technique can reduce the conversion cycles by 24% on average (maximum reduction of ~50%) with little digital overhead.

Ambient light interference is a significant hurdle as it creates unwanted DC current in optical receivers used for visible light communication, infrared communication, etc., that face solar irradiance in the daytime or unwanted light sources such as bulbs at night. This paper presents a current mirror-based receiver topology. By introducing a current-to-voltage converter module, the receiver can handily remove the background interference. A prototype receiver is designed using a 180 nm CMOS process operating at a speed of 160 MHz. It can cancel up to 100 µA of DC background interference while maintaining a low power dissipation of 7 mW from a 1.8 V supply. Additionally, it achieves a transimpedance gain of 120 dBΩ and an input referred noise of 10 pA/ Hz.

A sensor network is an underpinning infrastructure that enables various future IoT applications, such as precision agriculture, smart farm, and greenhouse monitoring. However, these sensor devices often suffer from short-lived battery lifetime that incurs frequent maintenance operation. Although there have been a few attempts to smartly reduce the power consumption associated with communication tasks of the sensors, very few have addressed the power consumption of sensing tasks. In light of this shortcoming, we propose an information-aware sensing framework that adaptively adjusts the sensing interval for energy-saving operations based on the learned behavior of the sensor data. To prove the effectiveness of the proposed framework, we have deployed four BLE beacons equipped with luminosity and temperature sensors to collect real-life data from a desert greenhouse, which is then used to train and evaluate our proposed framework. Additionally, we have implemented the proposed framework on a commodity BLE beacon device to validate the energy-saving performance of the proposed framework. The results demonstrate that the proposed framework can effectively reduce the energy consumption involved in sensing tasks by 30% and extend the battery lifetime by up to 75%.

In this paper, we present a system-level model for an ambient temperature-compensated CMOS MEMS Thermal Flow (C2MTF) sensor. The system-level model is first validated by a computational fluid dynamics (CFD) model and is further used for a fully coupled simulation between the microstructure, heat transfer, and interface circuits. Correspondingly, a monolithically integrated C2MTF sensor is designed and optimized using a 0.18 μm 1P6M CMOS MEMS technology. The designed System on Chip (SoC) C2MTF sensor has a flow range of -10~10 m/s, and its highest sensitivity is 0.274 V/(m/s) with a system power consumption of less than 3.6 mW. In comparison with the more than 50% output drift for the uncompensated counterpart, the output drift of the designed C2MTF sensor is reduced to 7% under an ambient temperature of 0~50 °C. In addition, based on the proposed system-level model, the additional optimizations show that the output drift can be greatly reduced to 0.5%, by arranging another on-chip overheated temperature-regulating resistor Rcin the future, delicately.

Abstract The licensed band is crowded and suffers from immense mobile data traffic growth, which exceeded 58 exabytes per month in 5 years. Meanwhile, a significant portion of the unlicensed band is underutilized and not coordinated efficiently. Experiments in some urban areas of the world have shown that only 5% of the unlicensed 5 GHz band is being used. 5G NR‐U technology supports 5G networks in the unlicensed band to alleviate the traffic congestion and boosts 5G networks capacity. Different heterogeneous network access technologies already use the unlicensed band. Consequently, 5G NR‐U networks will operate in the proximity of the other coexisting networks, such as WiFi networks in the 5 GHz and 6 GHz bands. In such environments, assessing the shared spectrum becomes challenging and necessitates adequate protocols to identify idle slots for successful transmissions. Cooperative Spectrum Sensing (CSS) improves the spectrum assessment process, as the decision about the spectrum state is rendered based on the local decisions of multiple sensing nodes. CSS is exploited by integrating it with Blockchain technology to design a decentralized cooperative spectrum management system called: Blockchain‐Based Cooperative Spectrum Management (BCSM). The system is attributed to ameliorating 5G NR‐U awareness about the neighboring WiFi networks traffic in the unlicensed band. An algorithm is designed for performing distributed cooperative spectrum assessment between the 5G NR‐U base stations to profile the WiFi networks traffic in their proximity. To ensure fairness based on the effort expended in assessing the spectrum, a priority‐based algorithm is designed for spectrum access scheduling. A proof‐of‐concept is implemented using private Ethereum Blockchain and NS3 simulator. Finally, the system's accuracy is evaluated empirically along with theoretical security analysis.

CMOS current readout is a critical circuit block for various applications like bio-sensing. This paper presents an overview of CMOS current readout techniques and analyze their merits and demerits, including noise floor, sensitivity, and achievable system bandwidth. Mainly, the practical applicability of individual technique/design for integrated low-noise bio-sensing applications is discussed. To present a thorough insight of the state-of-the-art, most recent and relevant articles published in the literature related to the current sensing interface are summarized and compared. The paper identified the primary DC current rejection schemes, where each approach and its limitations are discussed and shown that each system comes with its limits.

This paper proposes a power-up calibration scheme to mitigate the offset of a capacitive-gain chopper instrumentation amplifier (CCIA), thus suppressing the offset-induced output ripple. In this design, the first stage of the error amplifier is formed by multiple identical slices. Before normal operation, the offset polarity of each slice is determined by reusing the second stage of the amplifier as a comparator. With such polarity information, slices of the first stage are regrouped to achieve a statistical offset reduction. The proposed amplifier has been fabricated in a standard$0.18~\mu \text{m}$CMOS process with an area of 0.57 mm2, achieving an average peak-to-peak output ripple of 58 mV. The amplifier consumes$1.53~\mu \text{W}$with a 1.2 V supply. Compared to the state-of-the-art, the calibration time of the proposed scheme is much shorter (14 clock cycles) and the overhead logic consumes no static power after calibration. In addition, the slicing technique provides an extra degree of freedom to the amplifier for bandwidth and noise scaling.

An energy harvesting (EH) system is proposed to extract energy from a centimeter-scale electromagnetic (EM) micro wind turbine. To improve the end-to-end efficiency, an autonomous and self-biased active rectifier is employed. A hysteresis-controlled boost converter is designed with self-zero-current-switching calibrations, which achieves a peak DC-DC efficiency of 93.3% with a maximum efficiency improvement of 12.7%. In addition, a novel frequency-to-amplitude conversion (FAC) maximum power point tracking (MPPT) method is proposed for a cycle-to-cycle MPPT. In measurements, the proposed FAC MPPT requires no more than three cycles to locate the maximum power point (MPP) in abrupt frequency changes, with an 80% tracking accuracy in the first turbine cycle. In wind-field testing, the EH system starts to track the MPP one cycle after start-up at 2.0 V. In the steady-state, the EH system maintains its cycle-to-cycle MPP under different wind conditions. In wind-field testing for wind speeds from 1.0 to 5.0 m/s, the peak MPPT accuracy is 99.27%, with an MPPT efficiency of 99.85%. The extracted power is from 0.1 to 8 mW with a peak end-to-end efficiency of 88.2%. Compared to a full-bridge rectifier, a 630% energy extraction gain is measured at a low wind speed of 1.2 m/s. To the best of the authors' knowledge, this is the first IC prototype for a cm-scale EM wind turbine EH to achieve a cycle-to-cycle MPPT with the highest reported MPPT efficiency.

This paper presents the time-domain analysis of a fully differential incremental ΔΣ modulator. Particularly, the influence of the bipolar feedback signal on the quantization noise of the modulator is analyzed, which is overlooked in most IDC designs. Based on the analysis, an initial feedback zeroing scheme is introduced to decrease the quantization noise of the modulator. Moreover, the maximum number of output codeword that can be produced by the modulator is mathematically derived. Following the derivation, a control scheme is proposed to achieve 1.5-bit effective feedback without changing the quantizer and D/A topology. By applying the initial feedback zeroing and 1.5-bit feedback technique, quantization noise of the 1st- and 2nd-order modulators analyzed in this paper can be decreased by 4×, with very minor modifications on the modulator's original digital controllers.

“Fail often to succeed sooner” is a common mantra that we are told is the secret to success. When reporting research results, however, scholars rarely write about their failed attempts and only focus on the successful ones. Perhaps the source of this disconnect between what we preach and what we do can be found in the underlying assumption that published work is meant to move the field forward and failed attempts supposedly do not. The goal of the confessions presented in this paper is to show that even failed attempts are genuine and valuable contributions to our field provided that we learn from our mistakes and correct them. The 27 confessions span from planning oversights, digital and analog design errors, misunderstanding of devices, overlooked parasitics, LVS errors, and troubles in testing.

This paper investigates printing functional materials on diverse flexible substrates for rapid detection of volatile organic compounds (VOCs). Inkjet printing and doctor blade coating is performed for rapid manufacturing of the sensing devices. The three different substrates selected are polyethylene terephthalate (PET), cotton fabric and a common A4 type printing paper. The structural and morphological properties of the substrates are exploited to compare the detection of three different types of VOCs, such as acetone, ethanol and isopropanol. A silver (Ag) nanoparticles-based ink at suitable properties for inkjet printer is used for developing the interdigital electrodes. A nanocomposite of Carbon-based paste is applied as sensing layer. Geometrical parameters of the devices, materials, processing and sintering conditions are kept similar, to only explore the distinguished sensing capabilities based on the substrate materials. Two different concentrations i.e. 4 and 22 ppm (parts per million) of the representative VOCs are applied in the test chamber and corresponding chemoresistance values are recorded using a sourcemeter. The different resistance peak values and responses times are correlated with the type of substrates and a comparative study is performed based on the type of substrate. This research presents greater contribution in the field of large area, cost-effective and wearable VOCs sensors that are highly demanding both for industrial as well as environmental monitoring. Some of these VOCs are considered as potential bioanalytes, which can be used in the recognition of several chronic diseases using these wearable sensing devices.

This paper presents a chopper instrumentation amplifier design that employs a proposed amplifier slicing technique for offset reduction. In this scheme, the core amplifier is split into multiple identical slices. During operation, the offset polarity of these slices is firstly determined by employing the second-stage of the amplifier as a static comparator. Next, by using the polarity information, the amplifier slices are regrouped to achieve statistical offset suppression. A mathematical model is developed in this paper to estimate the effectiveness of this reduction scheme. The sliced amplifier structure also enables a scalable noise and bandwidth without adding extra analog components. Simulation results show that the proposed reduction scheme achieves a > 40 dB offset suppression and a noise efficiency factor (NEF) of 2.2. The circuit is implemented in a 0.18 μm standard CMOS technology for proof of concept and consumes 0.4 μA to 1 μA current from a 1.2 V supply to reach a noise level from 90 nV/√Hz to 31.8 nV/√Hz, respectively.

In this paper, a piecewise bipolar junction transistor (BJT) process spread compensation scheme is presented. By exploiting the strong correlation between the BJT saturation current and the piecewise base recombination current, the process spread and proportional-to-absolute-temperature (PTAT) drift of the base-emitter voltage (Vbe) can be reduced over a wide temperature range. Fabricated in standard 0.18-μm CMOS, the chip prototype achieves a measured Vbe standard deviation (STD) of 1.1 mV (1.8 mV) from -30 to 60 °C (-30 to 120 °C) over 12 samples, corresponding to a 2.9X (1.8X) improvement when compared to the measured Vbe STD of 3.24 mV at 25 °C from 15 standalone BJT samples with constant external bias current using the same process.

A micro-power incremental delta-sigma (I-ΣS) ADC is presented. This ADC uses its decimation filter's output to estimate the input signal level and dynamically adjusts the modulator feedback voltage, thereby reducing the integrator input range and power. For further power saving, integrator time-multiplexing is also employed. Fabricated in 0.18μm CMOS, the 0.12mm2 ADC consumes 2.16μW at a conversion speed of 85S/s, 15.3b resolution and -2/1.5LSB INL.

Planned Sensor Distortion (PSD) is a compression method that quantizes shifted signal with low bit depth. In this paper, we analyze the dynamic range loss issue in the PSD algorithm and propose two novel methods to overcome this issue: a blocked PSD, which divides the image into sub-blocks that adapt to pixel values, and an auto-reset PSD, which utilizes Markov property to recover a high dynamic range image from the modulo image. Simulation on a 3-bit depth image of indoor environment shows PSNR of 35.7dB and 35.0dB respectively after reconstruction using our algorithms. Thereafter, two different implementations for PSD are proposed, introducing shifts at either reset phase or readout phase. These circuits are then extended to be compatible with our proposed algorithms. Finally, simulation results using 0.18um GlobalFoundries process validate our designs. Spontaneous power optimization of ADC and transmission, hardware friendly feature, and the ability of high quality imaging make our compression method promising.

Wireless sensor network applications typically include various sensors (temperature, humidity, gas, etc.) and each sensor has different requirements of speed, noise, offset, and power consumption. In order to optimize the performance and allow long-time operation, reconfigurability is mostly desirable in the readout circuitry. In this paper, a reconfigurable time-domain comparator (RTDC) with low noise and low offset is proposed, mainly for reconfigurable SAR ADCs in wireless sensor nodes. With a supply voltage of 1.8 V, it can be dynamically reconfigured to operate in seven different modes for different sensing scenarios. From Mode 1 to Mode 7, the maximum operating speed of the comparator ranges from 182 MHz to 20 MHz with its input referred noise been reduced exponentially from 142 μV to 63.4 μV and its offset been reduced exponentially from 7.64 mV to 2.55 mV, respectively. The simulated energy efficiency is 1.27 pJ/conv in Mode 1 and it linearly increases to 9.48 pJ/conv in Mode 7. This wide operating range enables the best possible trade-off for the sensing node application at hand.

A sigma delta (ΣΔ) ADC for sensing application is presented in this paper. Several techniques are adopted to implement a low power high dynamic range ADC. Firstly, a single-stage inverter replaces the commonly used differential amplifier, in order to reduce the static current. Secondly, the normal NMOS transistor in the inverter stage is replaced by a high threshold device. As a result, with the same transistor size and supply voltage, the gain of the inverter can be enhanced while the short circuit current can be reduced. Thirdly, the charge leakage due to the forward-based parasitic diode is eliminated by using a charge protection switch and rearranged reference scheme. The proposed ΣΔ ADC is implemented and fabricated using TSMC 0.18μm technology. The simulation result shows that for a 1.8V supply, 25MHz sampling frequency and 125 oversampling ratio, the power consumption is 63.7μW and 116μW, dynamic range is 80dB and 83dB, the ENOB is 11.5 and 11.7bit for a single-ended and a pseudo-differential configurations, respectively. The presented ADC scheme can be applied in a Full HD image sensor running at up to 50 frames/s.

In this paper, a smart temperature sensor working at a supply voltage as low as 0.9V over the full military temperature range is presented. Low voltage operation is achieved by biasing the front-end BJT pairs with different emitter currents for two different sensing ranges, from -55°C to 30°C and from 20°C to 125°C, respectively. A second-order inverter-based ΣΔADC with dynamic element matching (DEM) and input signal chopping to control the conversion error to within 0:2°C is used for digital readout. Front-end bias currents are selected during the design stage to minimize the induced sensing error. The proposed sensor is implemented using the TSMC 0.18μm 1P6M process. Simulation result shows that a +1°C=-0:1°C sensing error using one-point calibration can be achieved from -55°C to 125°C. At a sampling speed of 20 samples/s, the sensor consumes 3.4μA and 4.7μA in the low temperature range and the high temperature range, respectively.