Low-density parity-check (LDPC) code as a very promising error-correction code has been adopted as the channel coding scheme in the fifth-generation (5G) new radio. However, it is very challenging to design a high-performance decoder for 5G LDPC codes because their inherent numerous degree-1 variable-nodes are very prone to be erroneous. In this article, the problem is solved gracefully by developing a low-complexity check-node update function, greatly improving the reliability of check-to-variable messages. By further incorporating the proposed column degree adaptation strategy, our decoder could offer a 0.4dB performance gain over the existing ones. In addition, this article presents an efficient 5G LDPC decoder architecture. Benefiting the specific structure of 5G LDPC codes, layer merging, split storage method, and selective-shift structure are introduced to facilitate a significant reduction of decoding delay and area consumption. Implementation result on 90-nm CMOS technology demonstrates that the proposed decoder architecture yields an impressive improvement in throughput-to-area ratio, achieving up to 173.3% compared to conventional design.

This paper proposes a new finite precision iterative decoder for low-density parity-check (LDPC) codes. The proposed decoder, named Sign-Preserving Min-Sum (SP-MS), significantly improves the decoding performance compared to the classical Offset Min-Sum (OMS) decoder when messages are quantized on$q=2$, 3, or 4 bits. The particularity of the SP-MS decoder is that messages cannot take the 0 value, and can fully benefit from the$q$bits of precision. The optimization of the SP-MS decoder is investigated in the asymptotic limit of the code length using density evolution (DE). Our study shows that 3-bit SP-MS decoders can achieve the same error-correcting performance as 5-bit OMS decoders, and 2-bit SP-MS decoders outperform 3-bit OMS decoders. The finite-length simulations confirm the conclusions of the DE analysis for several LDPC codes. Our SP-MS decoder shows a signal-to-noise ratio (SNR) gain up to 0.43 dB, with a memory/wire reduction of up to 40%, compared to the OMS decoder. Moreover, the SP-MS decoder converges faster and uses fewer iterations than the OMS decoder, with an improvement of up to 83.3% of the average decoding throughput. On an FPGA, the SP-MS decoder reduces resource utilization by up to 56% compared to the OMS decoder.

In this paper, we present a computationally efficient method for estimating error floors of low-density parity-check (LDPC) codes over the binary symmetric channel (BSC) without any prior knowledge of its trapping sets (TSs). Given the Tanner graph G of a code, and the decoding algorithm V, the method starts from a list of short cycles in G, and expands each cycle by including its sufficiently large neighborhood in G. Variable nodes of the expanded sub-graphs EXP are then corrupted exhaustively by all possible error patterns, and decoded by V operating on EXP. Union of support of the error patterns for which V fails on each EXP defines a subset of variable nodes that is a TS. The knowledge of the minimal error patterns and their strengths in each TSs is used to compute an estimation of the frame error rate. This estimation represents the contribution of error events localized on TSs, and therefore serves as an accurate estimation of the error floor performance of V at low BSC cross-over probabilities. We also discuss trade-offs between accuracy and computational complexity. Our analysis shows that in some cases the proposed method provides a million-fold improvement in computational complexity over standard Monte-Carlo simulation.

This paper presents an Enhanced Offset Min-Sum (EOMS) decoder for Low-Density Parity-Check (LDPC) codes used in the 5th generation (5G) mobile communications. It is observed that a significant part of Variable Nodes (VNs) in the 5G LDPC codes are with degree-1 and are very sensitive to be erroneous, leading to the fact that the decoding performance is generally reduced. In the EOMS decoding, the core check nodes (CN) and extension CNs are processed with different update rules. A new CN -update criterion is also proposed by making use of the third minimum value. As a result, the offset factors are adaptively selected and the error probability of degree-1 VNs is significantly reduced. Simulation results show that the proposed EOMS decoder offers a much better error-correction performance than the state-of-the-art benchmarks for several 5G LDPC codes with a negligible complexity overhead.

This paper presents the jointly use of constraint code (CC) and error correction codes (ECC) for the reliability enhancement in Multi-level cell NAND flash memories. In the proposed system, the constraint code helps transform the user data distribution, adapting to the asymmetry in error behavior of MLC NAND flash memories and the ECC corrects more errors thanks to the prior information from the data distribution. The compatibility of CC and ECC is analyzed, and the information loss is shown to be negligible, especially for the use in MLC NAND flash memories. Simulation under practical MLC NAND flash error model has shown that the proposed scheme can improve remarkably output error rate and reduce read latency in these memories.

This paper presents an adaptation of the Min-Sum decoders for the Low-Density Parity-Check (LDPC) used in the enhanced mobile broadband (eMBB) scenario in the 5th generation mobile networks (5G). Starting from the structure of the proposed LDPC codes for 5G where a significant part of the Variable Nodes (VNs) is with degree-1 and is sensitively to be erroneous in the traditional Offset Min-Sum decoder, we adapt the Min-Sum decoding principle to decode these 5G LDPC codes, targeting to improve the error correction performance. The proposed decoder, named Adapted Min-Sum (AMS), processes the core and the extension parts of the code differently using different offset factors. By doing that, the error probability of degree-1 VN is significantly depressed. We show through the simulation performance that the proposed decoder, with small number of quantization bits, can even surpass the floating-point counterpart and approaches the performance of the Sum-Product decoder for several 5G LDPC code lengths and code rates, with negligible additional complexity.

The Probabilistic Gradient Descent Bit-Flipping (PGDBF) decoder offers a significant improvement in decoding performance for Low-Density Parity-Check (LDPC) codes on Binary Symmetric Channel (BSC). However, this outstanding decoding performance comes along with a non-negligible extra hardware cost to realize the probabilistic behavior on top of the deterministic Gradient Descent Bit-Flipping (GDBF) decoder. This paper presents a novel solution to implement PGDBF decoder on Quasi-Cyclic LDPC codes. The proposed architecture takes advantage of the cyclic shift permutation nature of QC-LDPC and changes the message flow such that a probabilistic behavior is emulated without the cost of an actual probabilistic signal generator. It is shown that, the proposed architecture improves the PGDBF decoding performance with respect to the state-of-the-art implementation while reducing hardware complexity, even being lower than that of the deterministic GDBF. The efficiency of our proposed method is verified through the ASIC 90nm CMOS technology implementations and decoding simulations.

This paper proposes a generalization of the recently introduced successive cancellation flip (SCFlip) decoding of polar codes, characterized by a number of extra decoding attempts, where one or several positions are flipped from the standard SC decoding. To make such an approach effective, we first introduce the concept of higher order bit flips and propose a new metric to determine the bit flips that are more likely to correct the trajectory of the SC decoding. We then propose a generalized SCFlip decoding algorithm, referred to as dynamic-SCFlip (D-SCFlip), which dynamically builds a list of candidate bit flips, while guaranteeing that the next attempt has the highest probability of success among the remaining ones. Simulation results show that D-SCFlip is an effective alternative to SC-list decoding of polar codes, by providing very good error correcting performance, with an average computation complexity close to the one of the SC decoder.

This paper introduces a new approach to cost-effective, high-throughput hardware designs for low-density parity-check (LDPC) decoders. The proposed approach, called nonsurjective finite alphabet iterative decoders (NS-FAIDs), exploits the robustness of message-passing LDPC decoders to inaccuracies in the calculation of exchanged messages, and it is shown to provide a unified framework for several designs previously proposed in the literature. NS-FAIDs are optimized by density evolution for regular and irregular LDPC codes, and are shown to provide different tradeoffs between hardware complexity and decoding performance. Two hardware architectures targeting high-throughput applications are also proposed, integrating both Min-Sum (MS) and NS-FAID decoding kernels. ASIC post synthesis implementation results on 65-nm CMOS technology show that NS-FAIDs yield significant improvements in the throughput to area ratio, by up to 58.75% with respect to the MS decoder, with even better or only slightly degraded error correction performance.

Lowering the power supply of a circuit can induce transient errors in the memory cells and timing errors in the computation units. In this paper, we consider the Taylor-Kuznetsov (TK) memory architecture with transient errors in the memory cells and with timing errors in the correction circuit. We provide a theoretical analysis of the performance of TK memories under transient errors and timing errors. Our study is based on the analysis of the computation trees of the equivalent Gallager B decoders with and without timing errors. As a main result, we show that as the number of iterations goes to infinity, the error probability of the decoder with timing errors converges to the error probability of the decoder without timing errors. Monte Carlo simulations confirm this result even for moderate code lengths.

Flash memories are gaining prominence for utilizing in large scale data centers (DCs) due to their high memory density, low power consumption and heat dissipation, and high access speed characteristics. The rate of degradation for a flash memory is largely affected by the amount and frequency of the erase/write operations, which is a challenge in the DC context that serves dynamically changing workloads. Adaptive Error Correction Code (AECC) schemes have been introduced for changing the error correction algorithm based on the reliability state of the flash. In this study we show that hard decision (bit-flipping) and soft decision decoding (Belief Propagation) class of algorithms for Low Density Parity Check (LDPC) decoders complement each other for utilizing in the flash based DCs in order to meet the dynamically changing reliability level. We propose a new family of ECC to improve the reliability of flash memory. Our Monte-Carlo simulations and Field Programmable Gate Array (FPGA) based hardware implementation analysis show that LDPC decoders are suitable for balancing the throughput, decoding performance and reliability requirements in DCs.

The Probabilistic Gradient Descent Bit-Flipping (PGDBF) decoder has been proposed as a very promising hard-decision Low-Density Parity-Check (LDPC) decoder with a large gain in error correction. However, this impressive decoding gain is reported to come along with a non-negligible extra complexity due to the additional Perturbation Block (PB) required on top of the Gradient Descent Bit-Flipping (GDBF) decoder. In this paper, an efficient solution to implement this PB is introduced which is shown to keep the decoding gain as good as the theoretical PGDBF decoder while requiring a very small hardware overhead compared to the non-probabilistic GDBF. The proposed architecture is designed basing on a statistical analysis conducted to find the key features of the randomness needed to maintain the decoding gain and to reveal the simplification directions. The efficiency of our proposed method is confirmed by the synthesis results of decoder implementations on ASIC with 65nm CMOS technology and performance simulations.

In this paper, we define Noise-against-Noise Min-Sum (NAN-MS) decoders as decoders that incorporate a certain amount of random perturbation due to deliberate noise injection. We introduce a noise model which is used to implement quantized NAN-MS decoders, using a limited number of precision bits. The behavior of NAN-MS decoders is investigated in the asymptotic limit of the code length using a noisy version of density evolution (DE). We use the noisy-DE thresholds to analyze and optimize the noise model parameters. We show that a controlled injection of noise allows NAN-MS decoders to achieve better performance than noiseless MS decoders, especially for low precision. The finite-length simulations confirm the conclusions of the DE analysis.

Non-binary multi-edge type ensembles of low-density parity-check codes are analyzed in terms of non-binary codeword weight distribution and its growth rate. In particular, an exact expression of the growth rate for small weights is developed. As a side result, the stopping set distributions of these ensembles are developed. Examples of weight distributions are provided, showing that the derived closed-form expressions can be easily evaluated. The obtained results can thus be exploited to analyze and design non-binary low-density parity-check codes that fall within the multi-edge type framework such as, but not limited to, protograph-based codes.

In this paper, we propose a layered LDPC decoder architecture targeting flexibility, high-throughput, low cost, and efficient use of the hardware resources. The proposed architecture provides full design time flexibility, i.e., it can accommodate any Quasi-Cyclic (QC) LDPC code, and also allows redefining a number of parameters of the QC-LDPC code at the run time. The main novelty of the paper consists of: (1) a new low-cost processing unit that merges the logical functionalities of the Variable-Node Unit (VNU) and the A Posteriori Log-Likelihood Ratio (AP-LLR) unit in an efficient way, (2) a high speed, low-cost Check-Node Unit (CNU) architecture, which is executed twice at each iteration in order to complete the computation of the check-node messages, (3) a splitting of the iteration processing in two perfectly symmetric stages, executed in two consecutive clock cycles, each one using exactly the same processing resources, the processing load is perfectly balanced between the two clock cycles, thus yielding an optimal clock frequency. Synthesis results targeting a 65nm CMOS technology for a (3,6)-regular (648,1296) Quasi-Cyclic LDPC code and for the WiMax (1152,2304) irregular QC-LDPC code show significant improvements in terms of area and throughput compared to the baseline architecture discussed in this paper, as well as several state of the art implementations.

This paper focuses on the recently introduced Successive Cancellation Flip (SCFlip) decoder of polar codes. Our contribution is twofold. First, we propose the use of an optimized metric to determine the flipping positions within the SCFlip decoder, which improves its ability to find the first error that occurred during the initial SC decoding attempt. We also show that the proposed metric allows closely approaching the performance of an ideal SCFlip decoder. Second, we introduce a generalisation of the SCFlip decoder to a number of ω nested flips, denoted by SCFlip-ω, using a similar optimized metric to determine the positions of the nested flips. We show that the SCFlip-2 decoder yields significant gains in terms of decoding performance and competes with the performance of the CRC-aided SC-List decoder with list size L=4, while having an average decoding complexity similar to that of the standard SC decoding, at medium to high signal to noise ratio.

LDPC decoders on faulty hardware have received increasing attention over the last few years, mainly motivated by reliability issues in emerging nanotechnologies. As a main result, it was shown that LDPC decoders are naturally robust to hardware faults. LDPC encoders on faulty hardware have received less attention, and they are expected to be less robust to hardware faults. In this work, we propose an LDPC encoding solution that is robust to faulty hardware. Our encoding solution is composed of two steps. First, an Augmented Encoding method is proposed, which consists in computing an augmented codeword that contains both the codeword to be transmitted on the channel and extra parity bits. The augmented codeword is computed from a noisy encoding circuit, and then corrected by a noisy Gallager-B decoder before channel transmission. The augmented codeword is obtained from a rate-compatible construction that guarantees good decoding performance both for the augmented codeword and for the codeword to be transmitted on the channel. In order to further improve the robustness of our encoding solution, we propose a second step, consisting of a circuit-level optimization. We propose to identify the critical gates that are responsible for encoding failures, and to duplicate them in order to reduce their influence on encoding outputs. Based on Monte-Carlo simulation, we show that the proposed solution significantly improves the encoding robustness to hardware faults.

This paper introduces a new theoretical framework, akin to the use of imprecise message storage in Low Density Parity Check (LDPC) decoders, which is seen as an enabler for cost-effective hardware designs. The proposed framework is the one of Non-Surjective Finite Alphabet Iterative Decoders (NS-FAIDs), and it is shown to provide a unified approach for several designs previously proposed in the literature. NS-FAIDs are optimized by density evolution for WiMAX irregular LDPC codes and we show they provide different trade-offs between hardware complexity and decoding performance. In particular, we derive a set of 27 NS-FAIDs that provide decoding gains up to 0.36 dB, while yielding a memory/interconnect reduction up to 25%/30% compared to the Min-Sum decoder.

We propose an iterative decoder made of a combination of faulty and perfect logic gates that is capable of correcting more channel errors than its counterpart made completely of perfect logic gates. We present an error probability analysis based on absorbing Markov chains, and explain how the randomness in the check node update function helps a decoder to escape to local minima associated with trapping sets. For the (155, 64) Tanner low-density parity check code, we provide a range of gate failure probabilities for which imperfect decoders perform better.

In this paper, several implementations of the recently introduced PGDBF decoder for LDPC codes are proposed. In [2], the authors show that using randomness in bit-flipping decoders can greatly improve the error correction performance. In this paper, two models of random generators are proposed and compared through hardware implementation and performance simulation. A conventional implementation of the random generator through LFSR as a first design, and a new approach using binary sequences that are produced by the LDPC decoder, named IVRG, as second design. We show that both implementation of the PGDBF improve greatly the error correction performance, while maintaining the same large throughtput. However, the performance gain requires a large hardware overhead in the case of LFSR-PGDBF, while the overhead is limited to only 10% in the case of the IVRG-PGDBF.

In this paper, we propose a predictive method to construct regular column-weight-three LDPC codes with girth g = 8 so that their Tanner graphs contain a minimum number of small trapping sets. Our construction is based on improvements of the Progressive Edge-Growth (PEG) algorithm. We first show how to detect the smallest trapping sets (5; 3) and (6; 4) in the computation tree spread from variable nodes during the edge assignment. A precise and rigorous characterization of trapping sets (5; 3) and (6; 4) are given, and we then derive a modification of the Randomized Progressive Edge-Growth (RandPEG) algorithm [1] to take into account a new cost function that allows to build regular column-weight dv= 3, girth 8 LDPC codes free of (5,3) and with a minimization of (6,4). We present the construction and the performance results in the context of quasi-cyclic LDPC (QC-LDPC) codes.

The non-binary codeword weight distribution and its growth rate are developed for non-binary multi-edge type ensembles of low-density parity-check codes. Moreover, an analysis of the growth rate for small weights is provided. The derived expressions can serve as powerful and flexible tools to analyze and design the non-binary low-density parity-check codes that fall within the multi-edge type framework.

This paper addresses the problem of designing low-density parity check decoders robust to transient errors introduced by faulty hardware. We assume that the faulty hardware introduces errors during the message-passing updates, and we propose a general framework for the definition of the message update faulty functions. Within this framework, we define symmetry conditions for the faulty functions and derive two simple error models used in the analysis. With this analysis, we propose a new interpretation of the functional density evolution threshold introduced by Kameni et al. in the recent literature and show its limitations in the case of highly unreliable hardware. However, we show that under restricted decoder noise conditions, the functional threshold can be used to predict the convergence behavior of finite alphabet iterative decoders (FAIDs) under faulty hardware. In particular, we reveal the existence of robust and nonrobust FAIDs and propose a framework for the design of robust decoders. We finally illustrate robust- and nonrobust-decoder behaviors of finite-length codes using Monte Carlo simulations.

This paper investigates the behavior of the Min-Sum decoder running on noisy devices. Our aim is to evaluate the robustness of the decoder to computation noise caused by the faulty logic in the processing units. This type of noise represents a new source of errors that may occur during the decoding process. To this end, we first introduce probabilistic models for the arithmetic and logic units of the finite-precision min-sum decoder and then carry out the density evolution analysis of the noisy min-sum decoder. We show that, in some particular cases, the noise introduced by the device can help the min-sum decoder to escape from fixed points attractors and may actually result in an increased correction capacity with respect to the noiseless decoder. We also point out a specific threshold phenomenon, referred to as functional threshold, which accurately describes the convergence behavior of noisy decoders. The behavior of the noisy MS is demonstrated in the asymptotic limit of the code length through a noisy version of density evolution and is also verified in the finite-length case by Monte Carlo simulations.

Nonbinary low-density parity-check (NB-LDPC) codes have become an efficient alternative to their binary counterparts in different scenarios, such as moderate codeword lengths, high-order modulations, and burst error correction. Unfortunately, the complexity of NB-LDPC decoders is still too high for practical applications, especially for the check node (CN) processing, which limits the maximum achievable throughput. Although a great effort has been made in the recent literature to overcome this disadvantage, the proposed decoders are still not ready for high-speed implementations for high-order fields. In this paper, a simplified trellis min-max algorithm is proposed, where the CN messages are computed in a parallel way using only the most reliable information. The proposed CN algorithm is implemented using a horizontal layered schedule. The overall decoder architecture has been implemented in a 90-nm CMOS process for a (N = 837 and K = 726) NB-LDPC code over GF(32), achieving a throughput of 660 Mb/s at nine iterations based on postlayout results. This decoder increases hardware efficiency compared with the existing recent solutions for the same code.

In this paper, we propose a new approach to constructing a class of check-hybrid generalized low-density parity-check (GLDPC) codes which are free of small trapping sets. This approach is based on converting selected checks of an LDPC code involving a trapping set to super checks corresponding to a shorter error correcting component code. In particular, we follow two goals in constructing the check-hybrid GLDPC codes: First, the super checks are replaced based on the knowledge of trapping sets of the global LDPC code. We show that by converting only some single checks to super checks the decoder corrects the errors on a trapping set and hence eliminates the trapping set. Second, the number of super checks required for eliminating certain trapping sets is minimized to reduce the rate-loss. We first give an algorithm to find a set of critical checks in a trapping set of an LDPC code and then we provide some upper bounds on the minimum number of critical checks needed to eliminate certain trapping sets in the parity-check matrix of an LDPC code. A possible fixed set for a class of check-hybrid codes is also given.

Generalized belief propagation (GBP) is known to be a well-suited technique for approximate inference problems in loopy factor graphs. It can absorb problematic subgraphs inside regions to reduce their influence on the inference. However, the choice of regions to be used in GBP remains a delicate issue. This paper proposes an approach to create specific regions when dealing with Low-Density Parity-Check (LDPC) codes. We split trapping sets, known to degrade the decoding performance, to make GBP locally optimal. Experiments show that GBP can then perform better than BP, especially in the error-floor region.

A multiple-vote symbol-flipping (MV-SF) decoding algorithm for nonbinary low-density parity-check (NB-LDPC) codes is proposed in this paper. Our algorithm improves the generalized bit-flipping algorithm (GBFDA) by considering the multiplicity of the candidates at the check-node output, to perform a more accurate symbol-flipping decision at the variable node update. The MV-SF algorithm greatly improves the frame error rate performance of GBFDA and approaches the performance of the best state-of-the-art decoders [extended min-sum and min-max (Min–Max)] with lower complexity. For a$(N=837,K=723)$NB-LDPC code over GF(32), the decoder derived from the proposed algorithm can reach a throughput higher than 500 Mb/s and a coding gain of 0.44 dB compared with the most efficient GBFDA architecture with only twice the silicon area. Our architecture has 27% efficiency gain compared with the best Min–Max architecture found in the literature, with a performance loss of just 0.21 dB at frame error rate$10^{-4}$.

We consider Incremental Redundancy Hybrid Automatic Repeat reQuest (IR-HARQ) in which the code rate and modulation of the initial transmission and all retransmissions are adjusted based on average channel statistics. In the absence of instantaneous channel state information at the transmitter (CSIT), we present a method which computes, prior to transmission, the optimum code rates and modulations and explicitly considers a given maximum number of retransmissions. For the case that additional feedback on CSI of previous transmission attempts is available, we present two heuristic schemes which exploit this knowledge and offer increased throughput at the cost of higher computational complexity. We employ a rate-adaptive non-binary LDPC coding scheme which makes use of non-binary repetitions. While this coding scheme is particularly well-suited for adaptive IR-HARQ, we note that the presented analysis can be applied to any other channel code which employs soft decoding.

This paper deals with Low-Density Parity-Check decoders running on noisy hardware. This represents an unconventional paradigm in communication theory, since it is traditionally assumed that the error correction decoder operates on error-free devices and the randomness (in the form of noise and/or errors) exists only in the transmission channel. However, with the advent of nanoelectronics, it starts to be widely accepted that the future generations of circuits and systems will need to reliability compute and solve statistical inferences, by making use of unreliable “noisy” components. It is then critical to properly evaluate the robustness of the existing decoders in the presence of an additional source of noise at the circuit level. To this end, we first introduce a new error model approach and carry out the “noisy” density evolution analysis of the fixed-point Min-Sum decoding. Then, for different parameters of the noisy components of the decoder, we determine the range of the signal-to-noise ratio values for which the decoder is able to achieve a target bit error rate performance. Finally, we evaluate the finite-length performance of the Min-Sum and two other Min-Sum-based decoders running on noisy hardware.

Low-density parity-check (LDPC) codes are adopted in many applications due to their Shannon-limit approaching error-correcting performance. Nevertheless, belief-propagation (BP) based decoding of these codes suffers from the error-floor problem. Recently, a new type of decoders termed finite alphabet iterative decoders (FAIDs) were introduced. The FAIDs use simple Boolean maps for variable node processing. With very short word length, they can surpass the BP-based decoders in the error floor region. This paper develops a low-complexity implementation architecture for FAIDs by making use of their properties. Particularly, an innovative bit-serial check node unit is designed for FAIDs, and the symmetric Boolean maps for variable node processing lead to small silicon area. An optimized data scheduling scheme is also proposed to increase the hardware utilization efficiency. From synthesis results, the proposed FAID implementation needs only 52% area to reach the same throughput as one of the most efficient Min-sum decoders for an example (7807, 7177) LDPC code, while achieving better error-correcting performance in the error-floor region.

In this letter, we propose a compressive sensing scheme for the mixture estimation problem in spectroscopy. We show that by applying an appropriate measurement matrix on the chemical mixture spectrum, we obtain an overall measurement matrix which is sparse. This enables the use of a low-complexity iterative reconstruction algorithm, called the interval-passing algorithm, to estimate the concentration of each chemical present in the mixture. Simulation results for the proportion of correct reconstructions show that chemical mixtures with a large number of chemicals present can be recovered.

Recently, we introduced a new class of finite alphabet iterative decoders (FAIDs) for low-density parity-check (LDPC) codes. These decoders are capable of surpassing belief propagation (BP) in the error floor region on the binary symmetric channel (BSC) with much lower complexity. In this paper, we introduce a novel scheme with the objective of guaranteeing the correction of a given and potentially large number of errors on column-weight-three LDPC codes. The proposed scheme uses a plurality of FAIDs which collectively correct more error patterns than a single FAID on a given code. The collection of FAIDs utilized by the scheme is judiciously chosen to ensure that individual decoders have different decoding dynamics and correct different error patterns. Consequently, they can collectively correct a diverse set of error patterns, which is referred to as decoder diversity. We provide a systematic method to generate the set of FAIDs for decoder diversity on a given code based on the knowledge of the most harmful trapping sets present in the code. Using the well-known column-weight-three (155,64) Tanner code with dmin= 20 as an example, we describe the method in detail and show, by means of exhaustive simulation, that the guaranteed error correction capability on short length LDPC codes can be significantly increased with decoder diversity.

In this paper, we present an improvement and a new implementation of a simplified decoding algorithm for non-binary low density parity-check codes (NB-LDPC) in Galois fields GF(q). The base algorithm that we use is the Extended Min-Sum (EMS) algorithm, which has been widely studied in the recent literature, and has been shown to approach the performance of the belief propagation (BP) algorithm, with limited complexity. In our work, we propose a new way to compute modified configuration sets, using a trellis representation of incoming messages to check nodes. We call our modification of the EMS algorithm trellis-EMS (T-EMS). In the T-EMS, the algorithm operates directly on the deviation space by considering a trellis built from differential messages, which serves as a new reliability measure to sort the configurations. We show that this new trellis representation reduces the computational complexity, without any performance degradation. In addition, we show that our modifications of the algorithm allows to greatly reduce the decoding latency, by using a larger degree of hardware parallelization.

We introduce a new paradigm for finite precision iterative decoding on low-density parity-check codes over the binary symmetric channel. The messages take values from a finite alphabet, and unlike traditional quantized decoders which are quantized versions of the belief propagation (BP) decoder, the proposed finite alphabet iterative decoders (FAIDs) do not propagate quantized probabilities or log-likelihoods and the variable node update functions do not mimic the BP decoder. Rather, the update functions are maps designed using the knowledge of potentially harmful subgraphs that could be present in a given code, thereby rendering these decoders capable of outperforming the BP in the error floor region. On certain column-weight-three codes of practical interest, we show that there exist {FAIDs that surpass the floating-point BP decoder in the error floor region while requiring only three bits of precision for the representation of the messages}. Hence, FAIDs are able to achieve a superior performance at much lower complexity. We also provide a methodology for the selection of FAIDs that is not code-specific, but gives a set of candidate FAIDs containing potentially good decoders in the error floor region for any column-weight-three code. We validate the code generality of our methodology by providing particularly good three-bit precision FAIDs for a variety of codes with different rates and lengths.

This paper continues a previous work on non-binary cluster-LDPC codes. Such codes are defined by locally dense parity-check matrices, with (possibly rectangular) dense clusters of bits, but which are cluster-wise sparse. We derive a lower bound on the minimum distance of non-binary cluster-LDPC codes that is based on the topological properties of the underlying bipartite graph. We also propose an optimization procedure, which allows designing finite length codes with large minimum distance, even in the extreme case of codes defined by ultra-sparse graphs, i.e. graphs with all symbol-nodes of degree dv= 2. Furthermore, we provide asymptotic thresholds of ensembles of non-binary cluster-LDPC codes, which are computed exactly under the Belief Propagation decoding, and upper-bounded under the Maximum a Posteriori (MAP) decoding. We show that the MAP-threshold upper bounds, which are conjunctured to be tight, quickly approach the channel capacity, which confirms the excellent minimal distance properties of non-binary cluster-LDPC codes.

Finite alphabet iterative decoders (FAIDs) for LDPC codes were recently shown to be capable of surpassing the Belief Propagation (BP) decoder in the error floor region on the Binary Symmetric channel (BSC). More recently, the technique of decimation which involves fixing the values of certain bits during decoding, was proposed for FAIDs in order to make them more amenable to analysis while maintaining their good performance. In this paper, we show how decimation can be used adaptively to further enhance the guaranteed error correction capability of FAIDs that are already good on a given code. The new adaptive decimation scheme proposed has marginally added complexity but can significantly improve the slope of the error floor performance of a particular FAID. We describe the adaptive decimation scheme particularly for 7-level FAIDs which propagate only 3-bit messages and provide numerical results for column-weight three codes. Analysis suggests that the failures of the new decoders are linked to stopping sets of the code.

We introduce a generic approach, called FAID diversity, for improving the error correction capability of regular low-density parity check codes, beyond the belief propagation performance. The method relies on operating a set of finite alphabet iterative decoders (FAID). The message-passing update rules are interpreted as discrete dynamical systems, and are judiciously chosen to ensure that decoders have different dynamics on a specific finite-length code. An algorithm is proposed which uses random jumps in the iterative message passing trajectories, such that the system is not trapped in periodic attractors. We show by simulations that the FAID diversity approach with random jumps has the potential of approaching the performance of maximum-likelihood decoding for finite-length regular, column-weight three codes.

In this paper we analyze the performance of several bit-interleaving strategies applied to Non-Binary Low-Density Parity-Check (LDPC) codes over the Rayleigh fading channel. The technique of bit-interleaving used over fading channel introduces diversity which could provide important gains in terms of frame error probability and detection. This paper demonstrates the importance of the way of implementing the bit-interleaving, and proposes a design of an optimized bit-interleaver inspired from the Progressive Edge Growth algorithm. This optimization algorithm depends on the topological structure of a given LDPC code and can also be applied to any degree distribution and code realization. In particular, we focus on non-binary LDPC codes based on graph with constant symbol-node connection dv= 2. These regular (2, dc)-NB-LDPC codes demonstrate best performance, thanks to their large girths and improved decoding thresholds growing with the order of Finite Field. Simulations show excellent results of the proposed interleaving technique compared to the random interleaver as well as to the system without interleaver.

We study fountain codes transmitted over the binary-input symmetric-output channel. For channels with small capacity, receivers in fountain coding systems needs to collects many channel outputs to recover information bits. Since a collected channel output yields a check node in the decoding Tanner graph, the channel with small capacity leads to large decoding complexity. In this paper, we introduce a novel fountain coding scheme with non-binary LDPC codes. The decoding complexity of the proposed fountain code does not depend on the channel. Numerical experiments show that the proposed codes exhibit better performance than conventional fountain codes, especially for moderate number of information bits.

We study iterative receivers for joint decoding and channel-state estimation for transmission on block-fading channels of root- LDPC-coded signals. Root-LDPC codes are known to be most performant codes for block-fading channels, as their spacial "root" structure allows to get the full-diversity property. This property ensures a good error decoding performance of root LDPC codes, especially in contrast with the performance standard LDPC codes (having the maximum diversity equal to 1). However, as any channel code, root-LDPC codes also suffer from the diversity loss when the channel state information is not known at the receiver. In this work we propose a joint channel estimation- decoding scheme for root- LDPC codes that helps to overcome this problem and still to have the full-diversity.

Finite alphabet iterative decoders (FAID) with multilevel messages that can surpass BP in the error floor region for LDPC codes on the BSC were previously proposed in [1]. In this paper, we propose decimation-enhanced decoders. The technique of decimation which is incorporated into the message update rule, involves fixing certain bits of the code to a particular value. Under appropriately chosen rules, decimation can significantly reduce the number of iterations required to correct a fixed number of errors, while maintaining the good performance of the original decoder in the error floor region. At the same time, the algorithm is much more amenable to analysis. We shall provide a simple decimation scheme for a particularly good 7-level FAID for column-weight three codes on the BSC, that helps to correct a fixed number of errors in fewer iterations, and provide insights into the analysis of the decoder. We shall also examine the conditions under which the decimation-enhanced 7-level FAID performs at least as good as the 7-level FAID.

In this paper, we study the asymptotic minimum distance of non-binary cluster-LDPC codes whose subjacent binary parity-check matrix is composed of localized density of ones, concentrated in clusters of bits. A particular attention is given to cluster codes represented by ultra-sparse bipartite graphs, in the sense that each symbol-node is connected to exactly dv= 2 constraint-nodes. We derive a lower bound on the minimum distance of non-binary cluster-LDPC codes and we show that there exist ensembles of ultra-sparse codes whose minimum distance grows linearly with the code length (with probability going to 1 as the code length goes to infinity). This result is in contrast with “classical” non-binary LDPC codes based on graphs with strictly regular dv= 2 symbol-nodes, whose minimum distance grows at most logarithmically with the code length. We also show that one can build practical non-binary cluster-LDPC codes with various finite codeword lengths, whose minimum distance is close to the Gilbert-Varshamov bound.

Recently new message passing decoders for LDPC codes, called finite alphabet iterative decoders (FAIDs) were proposed. The messages belong to a finite alphabet and the update functions are simple boolean maps different from the functions used for the belied propagation (BP) decoder. The maps can be chosen using the knowledge of potential trapping sets such that the decoders surpass the BP decoder in the error floor. In this paper, we address the issue of selecting good FAIDs which perform well in the error floor for column weight three codes. We introduce the notion of noisy trapping set which is a generalization based on analyzing the local dynamic behaviour of a given FAID on a trapping set. Using this notion as the core, we provide an iterative greedy algorithm that outputs a set of candidate FAIDs containing potentially good decoders for any given code. To illustrate the appliance of the methodology on several codes, we show that the set of candidate FAIDs contains particularly good FAIDs for different codes with different rates and lengths.

In this paper, a new and promising framework, called "non-binary decoder diversity", is presented based on the observation that different non-binary Tanner graphs of the same binary code, decoded with a non-binary belief-propagation decoder, can have distinct convergence behaviors and fixed points. The goal of this work is to propose a decoder with linear complexity in the blocklength, and with performance close to maximum-likelihood decoding. This framework is especially interesting for binary codes which are dense or locally-dense, and for which the usual binary iterative decoders perform far from the optimum curves. By using the diversity brought by decoding distinct Tanner graphs of the same code, the proposed technique has very good decoding performance for three very different test cases which are known to be complex decoding problems: (i) near maximum-likelihood decoding (MLD) of BCH codes on the BPSK-AWGN channel, (ii) performance results which outperform bounded distance decoding of BCH codes over a binary symmetric channel (BSC), and finally (iii) decoding performance better than the BCJR-based turbo-decoder for parallel duo-binary turbo-codes.

We propose nonbinary LDPC codes concatenated with multiplicative repetition codes. By multiplicatively repeating the (2,3)-regular nonbinary LDPC mother code of rate 1/3, we construct rate-compatible codes of lower rates 1/6, 1/9, 1/12,.... Surprisingly, such simple low-rate nonbinary LDPC codes outperform the best low-rate binary LDPC codes so far. Moreover, we propose the decoding algorithm for the proposed codes, which can be decoded with almost the same computational complexity as that of the mother code.

In this paper, we discuss the combination of non-binary channel coding with higher-order modulation and MIMO transmission in the form of spatial multiplexing. In addition to the benefits of non-binary LDPC codes on the AWGN channel, we identify an inherent advantage for non-binary coding in multiple antenna schemes. By comparing binary and q-ary information processing at the receiver, we highlight the intrinsic advantages of non-binary coding. A performance comparison based on simulation results shows that, at similar system complexity, non-binary information processing can actually outperform the Shannon limit of its binary counterpart.

We propose non-binary LDPC codes concatenated with multiplicative repetition codes. To the best of the authors' knowledge, for the transmissions over the memoryless binary-input output-symmetric channels, 2m-ary the (2,dc)-regular LDPC code for m ~ 8 and dc≥ 3 is the best code so far among codes with moderate code length. By multiplicatively repeating the 2m-ary (2,3)-regular LDPC code of rate 1/3, we construct rate-compatible codes of lower rates 1/6,1/9,1/12,.... Surprisingly, such simple low-rate codes outperform the best low-rate binary codes so far.

In this paper, we propose a new class of quantized message-passing decoders for LDPC codes over the BSC. The messages take values (or levels) from a finite set. The update rules do not mimic belief propagation but instead are derived using the knowledge of trapping sets. We show that the update rules can be derived to correct certain error patterns that are uncorrectable by algorithms such as BP and min-sum. In some cases even with a small message set, these decoders can guarantee correction of a higher number of errors than BP and min-sum. We provide particularly good 3-bit decoders for 3-left-regular LDPC codes. They significantly outperform the BP and min-sum decoders, but more importantly, they achieve this at only a fraction of the complexity of the BP and min-sum decoders.

In this paper we design non-uniform bit-wise puncturing distributions for irregular non-binary LDPC (NB-LDPC) codes. The puncturing distributions are optimized by minimizing the decoding threshold of the punctured LDPC code, the threshold being computed with a Monte-Carlo implementation of Density Evolution. First, we show that Density Evolution computed with Monte-Carlo simulations provides accurate (very close) and precise (small variance) estimates of NB-LDPC code ensemble thresholds. Based on the proposed method, we analyze several puncturing distributions for regular and semi-regular codes, obtained either by clustering punctured bits, or spreading them over the symbol-nodes of the Tanner graph. Finally, optimized puncturing distributions for non-binary LDPC codes with small maximum degree are presented, which exhibit a gap between 0.2 and 0.5 dB to the channel capacity, for punctured rates varying from 0.5 to 0.9.

In this paper, we propose a new implementation of the Extended Min-Sum (EMS) decoder for non-binary LDPC codes. A particularity of the new algorithm is that it takes into accounts the memory problem of the non-binary LDPC decoders, together with a significant complexity reduction per decoding iteration. The key feature of our decoder is to truncate the vector messages of the decoder to a limited number nmof values in order to reduce the memory requirements. Using the truncated messages, we propose an efficient implementation of the EMS decoder which reduces the order of complexity to ¿(nmlog2nm). This complexity starts to be reasonable enough to compete with binary decoders. The performance of the low complexity algorithm with proper compensation is quite good with respect to the important complexity reduction, which is shown both with a simulated density evolution approach and actual simulations.

In this paper, a new class of low-density parity-check (LDPC) codes, named hybrid LDPC codes, is introduced. Hybrid LDPC codes are characterized by an irregular connectivity profile and heterogeneous orders of the symbols in the codeword. It is shown in particular that the class of hybrid LDPC codes can be asymptotically characterized and optimized using density evolution (DE) framework, and a technique to maximize the minimum distance of the code is presented. Numerical assessment of hybrid LDPC code performances is provided, by comparing them to protograph-based and multiedge-type (MET) LDPC codes. Hybrid LDPC codes are shown to allow to achieve an interesting tradeoff between good error-floor performance and good waterfall region with nonbinary coding techniques.

A class of two-bit message passing decoders for decoding column-weight-four LDPC codes over the binary symmetric channel is proposed. The thresholds for various decoders in this class are derived using density evolution. For a specific decoder, the sufficient conditions for correcting all error patterns with up to three errors are derived.

For a (lambda(x); rho(x)) standard irregular LDPC code ensemble, the growth rate of the average weight distribution for small relative weight omega is given by log(lambda'(0)rho'(1))omega + O(omega2) in the limit of code length n. If lambda'(0)rho'(1) < 1, there exist exponentially few code words of small linear weight, as n tends to infinity. It is known that the condition coincides with the stability condition of density evolution over the erasure channels with the erasure probability 1. In this paper, we show that this is also the case with multi-edge type LDPC (MET-LDPC) codes. MET-LDPC codes are generalized structured LDPC codes introduced by Richardson and Urbanke. The parameter corresponding lambda'(0)rho'(1) appearing in the conditions for MET-LDPC codes is given by the spectral radius of the matrix defined by extended degree distributions.

Non-binary LDPC codes are now recognized as a potential competitor to binary coded solutions, especially when the codeword length is small or moderate. More and more works are reported with good performance/complexity tradeoffs, which make non-binary solutions interesting for practical applications, such as 4G-wireless systems or DVB-like systems. In this paper, we show that proposing non-binary LDPC codes built on finite fields is actually a limitation, both from performance and implementation points of view. By considering non-binary codes on the general linear group, we show in particular that a slight performance improvement can be obtained, compared to Galois Field codes, with reasonable additional cost in the hardware implementation. The performance gain is quite small, but comes at a slight extra decoding cost, and is obtained by proper generalization of the code optimization techniques that are standard for non-binary LDPC codes on fields.

In this paper, the impulse method to determine the low weight profile of sparse codes is improved based on efficient probabilistic approaches for reliability based decoding that are adapted to this problem. As a result, compared with previous approaches, the same low weight profile can be obtained with a significant time reduction (for example from 30 hours to a few minutes) or more complete low weight profiles can be determined in the same amount of time.

In this paper, we address the problem of providing unequal error protection (UEP) with LDPC codes built on finite sets of order strictly greater than 2 (nonbinary codes). The main interest of providing UEP with nonbinary LDPC codes is that future standards are likely to prefer nonbinary coding schemes because of their better robustness to the codeword length and the modulation size. However, the problem of giving UEP properties with nonbinary LDPC codes is much more difficult than with binary LDPC codes. We present a first attempt to solve this difficult problem, based on LDPC codes built on finite groups. The framework and the basis about group LDPC codes are first presented in details, and the framework is used to give examples of UEP nonbinary LDPC codes that actually achieve different UEP properties at the bit level while the symbol error properties are kept equally protected.

The design of efficient rateless coding schemes for multicast applications in wireless environments is investigated. First, the rateless paradigm for non-ergodic channels is introduced by making use of the dynamic-decoding nature of rateless codes that allows them to adapt opportunistically the code rate to the channel realization (assumed unknown at the transmitter). The information theoretical limits of such codes can be interpreted in terms of the notion of outage capacity. Then, we consider a quasi-static Rayleigh-fading channel with perfect and imperfect channel state information (CSI) at the receiver. We show that the optimal consistent measure of information for decoding with imperfect CSI, is given by the log-likelihood ratio (LLR) of the received bits via a composite (more noisy) channel. The optimization of Raptor codes, which depends on the delay requirements of decoding, is obtained by using Information content evolution under Gaussian approximation. Simulation results show that optimized Raptor codes can operate very close to the theoretical limits on a wide range of delay requirements.

In this paper, we propose and study a new family of error-correcting codes. These achieve excellent error performance under an iterative decoding over the binary-input noisy channel and solves the memory space requirements problem of the non-binary LDPC decoders. We named this class of codes, Split non-binary LDPC codes. The main particularity of this new family of codes is that the variable and the check nodes are not defined over the same finite field GF(2p), like in the case of classical non-binary LDPC codes. The class of Split non-binary LDPC codes is obviously larger than that of existing types of codes, which gives more degrees of freedom to find good codes when the existing codes show their limits. We provide two examples of interesting split NB-LDPC codes.

In this paper, a method to design regular (2, dc)- LDPC codes over GF(q) with both good waterfall and error floor properties is presented, based on the algebraic properties of their binary image. First, the algebraic properties of rows of the parity check matrix H associated with a code are characterized and optimized to improve the waterfall. Then the algebraic properties of cycles and stopping sets associated with the underlying Tanner graph are studied and linked to the global binary minimum distance of the code. Finally, simulations are presented to illustrate the excellent performance of the designed codes.

In this paper, we propose a new implementation of the EMS decoder for non binary LDPC codes presented in (D. Declencq and M. Fossorier, 2007). A particularity of the new algorithm is that it takes into accounts the memory problem of the non binary LDPC decoders, together with a significant complexity reduction per decoding iteration. The key feature of our decoder is to truncate the vector messages of the decoder to a limited number nm of values in order to reduce the memory requirements. Using the truncated messages, we propose an efficient implementation of the EMS decoder which reduces the order of complexity to O(nmlog2nm), which starts to be reasonable enough to compete with binary decoders. The performance of the low complexity algorithm with proper compensation are quite good with respect to the important complexity reduction, which is shown both with a simulated density evolution approach and actual FER simulations.

This paper is eligible for the student paper award. In this paper, we analyse asymptotically a new class of LDPC codes called non-binary hybrid LDPC codes, which has been recently introduced in L. Sassatelli and D. Declerq [2006]. We use density evolution techniques to derive a stability condition for hybrid LDPC codes, and prove their threshold behavior. We study this stability condition to conclude on asymptotic advantages of hybrid LDPC codes compared to their non-hybrid counterparts.

This paper is eligible for the student paper award. In this paper, we present an analytical analysis of the convergence of raptor codes under joint decoding over the binary input additive white noise channel (BIAWGNC), and derive an optimization method. We use information content evolution under Gaussian approximation, and focus on a new decoding scheme that proves to be more efficient: the joint decoding of the two code components of the raptor code. In our general model, the classical tandem decoding scheme appears to be a sub-case, and thus, the design of LT codes is also possible.

In this letter, we address the problem of decoding nonbinary low-density parity-check (LDPC) codes over finite fields GF(q), with reasonable complexity and good performance. In the first part of the letter, we recall the original belief propagation (BP) decoding algorithm and its Fourier domain implementation. We show that the use of tensor notations for the messages is very convenient for the algorithm description and understanding. In the second part of the letter, we introduce a simplified decoder which is inspired by the min-sum decoder for binary LDPC codes. We called this decoder extended min-sum (EMS). We show that it is possible to greatly reduce the computational complexity of the check-node processing by computing approximate reliability measures with a limited number of values in a message. By choosing appropriate correction factors or offsets, we show that the EMS decoder performance is quite good, and in some cases better than the regular BP decoder. The optimal values of the factor and offset correction are obtained asymptotically with simulated density evolution. Our simulations on ultra-sparse codes over very-high-order fields show that nonbinary LDPC codes are promising for applications which require low frame-error rates for small or moderate codeword lengths. The EMS decoder is a good candidate for practical hardware implementations of such codes

We introduce a wide class of low-density parity-check (LDPC) codes, large enough to include LDPC codes over finite fields, rings, or groups, as well as some nonlinear codes. A belief-propagation decoding procedure with the same complexity as for the decoding of LDPC codes over finite fields is also presented. Moreover, an encoding procedure is developed

In this paper, we develop algebraic properties of regular (2, tr, N) non binary LDPC codes designed using their binary image. First, we characterize the algebraic properties of optimized rows of the parity check matrix H associated with a code, and then we study the algebraic properties of cycles and stopping sets associated with the underlaying Tanner graph

We present in this paper an architectural model for implementing parallel and scalable low-density parity-check (LDPC) decoders. This model has been developed for targeting field-programmable gate array devices and system-on-chip (SoC) platforms. We present first the motivations of investigating a new hardware model for regular and irregular LDPC decoders. The code flexibility, the memory usage optimization, and an easy hardware integration have been taken into account. The construction of a specific class of codes (hardware-constrained LDPC codes) is then presented. Parallelization and pseudorandomness constraints of codes are particularly detailed. A complete description of our parallel and scalable hardware model suitable for reprogrammable architectures is then given. Simulation results are presented showing the efficiency of this model with both (3,6) regular and irregular codes

In this paper, we develop a generalization of the minsum (MS) algorithm which not only performs additions without the need of channel estimation, but also with the two following objectives: (i) a complexity much lower than O(q2) so that finite fields of large order can be considered; and (ii) a small performance degradation compared with BP decoding. The first objective is achieved by introducing configuration sets, which allow to keep only a small number of meaningful values at the check node processing. The second objective is achieved by applying at the variable node processing the correction techniques of J. Chen and M. Fossorier, (2002) to the proposed algorithm

In the context of DS-CDMA transmissions, we study the average performance of a link adaptation strategy performed through dynamic rate and power adaptation based on the minimum user information rate maximization subject to a target bit error rate for erroneous frames. Analytical expressions and bounds for the average information rate per user are derived when a Rayleigh fading environment is assumed. When compared to a link adaptation strategy based on the total throughput maximization, simulation results show improved performance, supporting more users in the cell for a wide range of channel conditions.

This paper describes the optimization of LDPC codes for unequal error protection (UEP) transmission schemes. The method is based on a hierarchical optimization of the irregularity for each class within the codeword by maximizing the average data node degree with a given error sensitivity at a finite number of decoding iterations.

In this paper, we present a low complexity code design for the 2-user Gaussian multiple access channels. In order to analyze this multiuser MAC decoder, we formulate density evolution (DE) and study the stability condition of the fixed point corresponding to zero BER.

We present a modification of belief propagation that enables us to decode LDPC codes defined on high order Galois fields with a complexity that scales as p log/sub 2/ (p), p being the field order. With this low complexity algorithm, we are able to decode GF(2/sup q/) LDPC codes up to a field order value of 256. We show by simulation that ultra-sparse regular LDPC codes in GF(64) and GF(256) exhibit very good performance.

In this paper, a theoretical expression of the optimum non-Gaussian radar detector is derived from the non-Gaussian SIRP model (Spherically Invariant Random Process) clutter and a bayesian estimator of the characteristic function of the SIRP. The SIRP model is used to perform coherent detection and to modelize the clutter as a complex Gaussian process whose variance is itself a positive random variable (r.v.). The PDF of the variance characterizes the statistics of the SIRP and after performing a bayesian estimation of this PDF from reference clutter cells we derive the Bayesian Optimum Radar Detector (BORD) and its statistical asymptotic form without any knowledge about the statistics of the clutter. We evaluate BORD performance for an unknown target signal embedded in K-distributed clutter and compare with optimum detectors performance (such as Optimum K Detector - OKD - in K-distributed clutter).

We present an optimized channel coding scheme for OFDM transmitter. Traditional coding methods use regular codes, in the sense that each bit participates in the same way to the channel encoding. Our approach consists in using a priory assumption on the channel available at the transmitter in order to optimize the coding scheme. We have considered the irregular Gallager block codes in our study. Simulations provide evidence of the usefulness of our approach with a gain of 2 dB at a bit error rate equal to 10/sup -5/ for optimized irregular coding scheme compared to regular one.

We compare two structures for combined equalization/detection of linear codes over frequency selective channels. The structures come from different families of codes: convolutional codes on one hand and parity check block codes on the other hand. First, we show that the joint receiver process corresponds to an iterative belief propagation schedule on graphical representations. Then, we draw and comment upon the simulation results for various codes and channel choices.

In this paper, we address the problem of building reconstruction in high-resolution stereoscopic aerial imagery. We present a hierarchical strategy to detect and model buildings in urban sites, based on a global focusing process, followed by a local modeling. During the first step, we extract the building regions by exploiting to the full extent the depth information obtained with a new adaptive correlation stereo matching. In the modeling step, we propose a statistical approach, which is competitive to the sequential methods using segmentation and modeling. This parametric method is based on a multiplane model of the data, interpreted as a mixture model. From a Bayesian point of view the so-called augmentation of the model with indicator variables allows using stochastic algorithms to achieve both model parameter estimation and plane segmentation. We then report a Monte Carlo study of the performance of the stochastic algorithm on synthetic data, before displaying results on real data.

A major problem with multicarrier transmissions is the near Gaussian behavior of the data stream entering the high power amplifier (HPA). This causes distortion (some samples are clipped) that must be corrected at the transmit-or receive-end, in order to improve the detection performance. We propose a new approach that recovers the distorted samples at the receiver. It is based on an "augmented" Bayesian model which captures the nonlinear behavior of the HPA. Estimates of the input symbols are then obtained with a hybrid deterministic/stochastic algorithm. Simulations over frequency selective channels show that when clipping is severe, our method outperforms existing methods.

We present some aspects of non-Gaussian H-ARMA models. After recalling that an H-ARMA process is obtained by passing an ARMA process through a Hermite polynomial nonlinearity, we describe the theoretical analysis of their cumulants and cumulant spectra. The main advantage of this kind of model is that the cumulant structure of the output can be deduced directly from the input covariance sequence. We give the analytic forms of these cumulants, together with some comments on their estimation. Then, we present the problems we are facing concerning the identification of the model's parameters, and give a first (and naive) method for their estimation. We give some results obtained on synthetic data and finally conclude with some remarks on this class of processes.

This paper introduces a new test statistic of normality which evaluates the cross covariances between choosen Hermite polynomials which are zero under the null hypothesis. The special form of the test leads to a modified sphericity statistic and we have called it the Hermite normality test (S/sub H/). We present its asymptotical distribution both under the null and nonnull hypothesis. A large number of simulations have been made to compare some specific Hermite tests to three others taken form the literature. If our test is better for a lot of nonnormal populations but works worse for some other, the main point is that we defined a wide range of tests which may match different nonnormal distributions.