In nanometer technologies the reliability of Static Random Access Memories (SRAMs) is seriously affected by transistor Bias-Temperature Instability (BTI). In this work, a circuit for the periodic aging monitoring in SRAM sense amplifiers (due to BTI related transistor degradation) is presented. This degradation increases the input offset voltage of a sense amplifier. Periodic monitoring provides the ability to avoid SRAM failures by detecting over aged sense amplifiers (near failure) and then properly react in order to maintain the memory reliable operation. The monitoring scheme is based on a low cost differential ring oscillator, which can be easily embedded in an SRAM array without affecting the normal mode of operation.

Transistor aging, due to Bias-Temperature Instability (BTI) is a serious concern in Static Random Access Memories (SRAMs). Under BTI stress an SRAM cell becomes increasingly skewed, which in turn affects its performance characteristics and consequently the memory reliability. In this paper, a variation tolerant technique for the periodic monitoring of the BTI influence on SRAM cells is presented. Periodic aging monitoring provides the ability to predict oncoming failures in the memory operation and react early to avoid them. The proposed scheme is based on the duty cycle monitoring of a low cost differential ring oscillator that can be easily embedded in a typical SRAM without affecting the normal mode of operation.

Due to their high density, modern DRAMs are very susceptible to the interactions between adjacent cells, which in turn increases the difficulty and complexity of memory testing. In this work, we studied the interaction mechanisms among neighbouring DRAM cells in order to provide an efficient testing solution. According to the open literature, there are two mechanisms responsible for this interaction: leakage currents and cell state transitions. The frequently used Coupling Fault (CF) model is inadequate to model the combined effect of these mechanisms, while testing procedures using the Neighborhood Pattern Sensitive Fault (NPSF) model are not time efficient solutions. Towards this direction, we propose a new fault model, the Neighborhood Leakage and Transition Fault (NLTF) model for DRAMs, which effectively models the faulty behavior related to neighbouring cell interference. In addition, we developed a new test algorithm which is based on the NLTF model, and provides test application time reductions ranging from 68 to 87 percent with respect to the existing testing algorithms in the literature that are capable to cover the NLTFs. Finally, the proposed algorithm is extended to cover NLTFs in word-oriented DRAMs.

The test complexity of high density DRAMs increases with technology evolution, due to a larger impact of process variation and weak defects. In particular, resistive open defects turn to be a major concern in DRAMs. Our analysis and simulation results show that an important phenomenon exists, charge accumulation, which is currently not considered in DRAM testing. Charge accumulation occurs in DRAM cells that suffer from internal resistive opens; a weak value stored at a cell is strengthened when a sequence of read operations is applied to it. Typical DRAM testing procedures (like March tests) fail to provide enhanced coverage of resistive open defects, since they do not consider charge accumulation. This paper provides an effective test algorithm that targets resistive open defects, while considering the bit-line imbalance and the charge accumulation mechanisms.

As dynamic random access memories (DRAMs) are becoming denser with technology scaling, more complex fault behaviors emerge; examples are leakage, coupling effects, and cell neighborhoods interaction. The neighborhood pattern sensitive fault (NPSF) model is suitable to address such faulty behaviors and identify them during the characterization and/or test of new DRAM chips. However, NPSF test algorithms are extremely time-consuming and therefore not economically affordable. In this brief, we show how layout information can be used to refine and significantly simplify the NPSF model and reduce the test time complexity. As a case study, the folded DRAM array is considered. A realistic NPSF model, the Δ-type neighborhood, is introduced together with a time efficient test algorithm which is more than two-times cheaper than traditional ones. Even when incorporating bit-line influence and word-line coupling effects, along with NPSFs, the test algorithm time complexity almost remains unaltered. Therefore, the proposed approach makes NPSF testing economically affordable, and hence, suitable for the characterization/test of dense DRAMs in the nanoera.

Although the Neighborhood Pattern Sensitive Fault (NPSF) model is recognized as a high quality fault model for memory arrays, the excessive test application time cost associated with it, compared to other fault models, restricts its wide adoption for memory testing. In this work we exploit the physical design (layout) of folded DRAM memory arrays to introduce a new neighborhood type for NPSF testing and a pertinent test and locate algorithm. This algorithm reduces drastically the test application time (about 58% with respect to the well known Type-1 neighborhood) aiming to make the NPSF model also a cost attractive choice. In addition, we introduce the Neighborhood Word-Line Sensitive Fault model and the corresponding test algorithm to cover those faults along with NPSFs, achieving test application time cost reduction from 33% to 41%, depending on various assumptions, with respect to the Type-1 neighborhood.