In multimedia applications, it is common to employ acoustic sensors collectively to enhance signals and to locate sound sources. A direct problem can be formulated to locate sound sources from a set of known sensors. In order to form the acoustic sensor network, it is important to locate the sensor array locations first. However, unlike other networks in which direct time-of-arrival (TOA) measurements might be possible, acoustic distributed network can only obtain time-difference-of-arrival (TDOA) measures indirectly from various sound source anchors. While it is common to employ convex optimization techniques to localize sensor locations in a network with TOA information, it has not been studied properly when it comes to TDOAs. This paper considers the microphone array localization problem in a distributed acoustic network with TDOA measurements. We formulate the inverse problem which applied the known source locations to identify the wireless array configuration and estimate the location for each array. The proposed method formulates a mixed semidefinite programming (SDP) and second-order cone programming (SOCP) relaxation model, and then the acoustic geometry is obtained by solving a linear optimal programming. Furthermore, the characteristics of the optimal solution are studied and exact relaxation conditions are given. Experimental results demonstrate that the proposed mixed model can successfully estimate the sensor locations in noisy and reverberant environments for 2-dimensional and 3-dimensional space, which outperforms other relaxation methods.

Building energy consumption accounts for a large figure of total energy consumption and keeps a rapid increase. Energy for heating, ventilation, and air conditioning (HVAC) is the main contribution. To save energy with maintaining comfort, control methods have been studied, including rule-based methods, model predictive control, and deep reinforcement learning (DRL). While their performance in real applications can be restricted by the highly nonstationary building environment caused by factors like weather conditions. Especially, for multizone HVAC control with multiple controllers, variation of the controller policy causes potential nonstationarity for each other. Current solutions to the nonstationarity based on model-based methods add complexity for building modeling and decrease the control efficiency. In addition, although massive data are available with the development of the Internet of Things (IoT) in smart buildings, high-level exploitation of data in the context-aware system is not yet explored to detect environment changes for smart building control. To this end, we propose a novel context-aware model-free DRL method called Trans-Context soft actor–critic (SAC) for multizone HVAC control, which combines a transformer-encoder-based context-aware system and the state-of-the-art DRL algorithm SAC. The context-aware system disentangles the nonstationarity by learning context data from IoT sensors. Besides, Trans-Context SAC is a model-free method without the need for building modeling. We evaluate Trans-Context SAC in a simulation-based case study on a multizone commercial building. Results demonstrate that Trans-Context SAC can achieve up to 15.9% of energy saving compared to other baselines with maintaining thermal comfort. Besides, Trans-Context SAC obtains the generalization for unseen environments.

We introduce the FGC Toolflow, the only tool providing flexible custom-FPGA generation and configuration to-date. Currently, researchers building custom FPGAs must create for FPGA schematics and bitstreams by hand. Both tasks are prohibitively time intensive and error prone. Additionally, the simulation time for bitcell configuration is very long (often times longer than the functionality), making the verification of FPGA fabrics even more time consuming. Some existing toolflows and software packages designed to help with this process, but they only generate bitcell configurations, leaving schematics to be developed by hand. Others have limitations in circuit-level and architectural parameters, which prevent them from adequately exploring the FPGA design space. The FGC flow is the only flow available that generates a custom full-FPGA schematic from a single parameter text file, and generates the proper configuration bitstream for a target Verilog functionality. The parameter text file can accommodate 100s of different parameters, which include both circuit-level and architectural parameters to fully encompass the FPGA design space. The FGC flow generates both a schematic and a configuration bitstream for an FPGA with 100 CLBs (900,000 transistors) in only 8 minutes. The flow also generates simulation files, allowing the user to quickly set up and perform simulations to verify the FPGA and its configuration at the chip level with SPICE-level accuracy. This flow was used to create, verify, and test a taped-out ultra-low power FPGA.

The rapid development of the Internet-of-Things requires hardware that is both low-energy and flexible, and a near/sub-threshold FPGA is a very promising solution. In the design of near/sub-threshold FPGAs, the biggest challenge is reducing global interconnect energy, which is the most energy-consuming part in the entire FPGA. Dynamic voltage scaling is an effective technique in reducing energy, but it is not widely used in FPGA interconnects because of the high area overhead of separately provisioning the buffers in the switch boxes to support different voltages on different paths. A low-swing interconnect, which removes buffers, allows this technique to be applied to the FPGA interconnects. In this paper, we propose a novel low-swing FPGA interconnect architecture that integrates dynamic voltage scaling and power-gating techniques with custom tool support. While the power-gating technique is widely used in existing designs for reducing leakage energy of idle drivers and buffers, we also apply power-gating to configuration bitcells in switch boxes, because it is a dominant energy consumer in near/sub-threshold. Including the energy overhead of voltage regulators, our work achieves a 10.1% energy saving in active circuits, 27.0% - 91.3% in idle circuits, and 19.0% - 53.1% in the entire FPGA on average, compared to an already optimized base case that only uses low-swing interconnect but no dynamic voltage scaling or power-gating. In addition, our dynamic voltage scaling allows us to adjust the delay of the low-swing FPGA interconnect from 0.14μs to 0.43μs or adjust its energy per operation from 5.5pJ to 35.7pJ when implementing the MCNC benchmarks at 0.6V.

Increased clustering in Field Programmable Gate Arrays (FPGAs) has shifted a larger fraction of the overall routing load into the configurable logic blocks (CLBs), reducing usage of the costly global interconnect. However, increases in CLB size introduce additional overheads inside CLBs, which can limit the savings gained by minimizing the global interconnect use, motivating more efficient intra-CLB routing. This paper explores different topologies for the intra-CLB connectivity and identifies how the optimal local-CLB interconnect changes for different FPGA architecture and circuit parameters. This work compares area, delay, and energy for two intra-CLB topologies: multiplexer-based routing and island-style bi-directional routing, similar to the global FPGA interconnect, but used inside the CLB (which we call a mini-FPGA). The mini-FPGA style of local CLB interconnect prove to be favorable for minimum-energy operation, as they can reduce transistor count by as much as 62%, and consume as much as 77.9% less energy. Multipexer-based CLBs have performance benefits by reducing delays by almost 3×. Multiplexer-based CLBs can consume less energy at nominal voltages, but only if additional measures are taken to limit power consumption in the multiplexers. A 130-nm CMOS test chip confirms that simulation results track measured data for mini-FPGA CLBs.

FPGA interconnect traditionally dominates energy and delay, and designs such as low-swing interconnect have been proven to reduce the interconnect burden for low energy FPGAs. This paper presents an optimized low-swing interconnect for FPGAs operating in the sub-threshold region. We also address signal degradation along lengthy interconnect paths and examine strategies for inserting low-switching-threshold repeaters. A 130nm test chip implementing low-swing interconnect meshes with different circuit parameters is measured. The results show that optimization of the low-swing interconnect provides up to 60.2% lower energy-delay-product (EDP) than a straightforward, un-optimized low-swing design at VDD= 0.4V. Furthermore, the simulation results show that the optimized low-swing interconnect is 97.7% faster and 42.7% lower energy than a traditional uni-directional interconnect at VDD= 0.4V.