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Simone Sbaraglia

dblp:73/1611 · DBLP profile ↗
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5ranked-venue papers
0as first author
0since 2021 · last 2008
0000-0003-2421-2801ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 5

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Performance modeling and evaluation · 74% Memory systems · 16% Embedded and real-time systems · 11%

Topics — the 7 heaviest of 8, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Performance modeling and evaluation
workload characterization
0.122005
Using Dynamic Tracing Sampling to Measure Long Running Programs · SC 2005
SIGMA: a simulator infrastructure to guide memory analysis · SC 2002
Performance modeling and evaluation › simulation
cache simulation
0.112005
Using Dynamic Tracing Sampling to Measure Long Running Programs · SC 2005
Performance modeling and evaluation
simulation
0.112005
Using Dynamic Tracing Sampling to Measure Long Running Programs · SC 2005
Memory systems
cache
0.122005
SIGMA: a simulator infrastructure to guide memory analysis · SC 2002
Using Dynamic Tracing Sampling to Measure Long Running Programs · SC 2005
Embedded and real-time systems › worst-case execution time analysis
cache analysis
0.012002
SIGMA: a simulator infrastructure to guide memory analysis · SC 2002
Performance modeling and evaluation › tracing
memory reference tracing
0.012002
SIGMA: a simulator infrastructure to guide memory analysis · SC 2002
Performance modeling and evaluation › simulation › simulation software
simulation infrastructure
0.012002
SIGMA: a simulator infrastructure to guide memory analysis · SC 2002

Methods — techniques the papers use, named apart from their topics

dynamic tracing sampling · 0.1software-based instrumentation · 0.0hardware performance counters · 0.0
YearPublicationVenuePosition
2008 A framework for automated performance bottleneck detection
abstract
In this paper, we present the architecture design and implementation of a framework for automated performance bottleneck detection. The framework analyzes the time-spent distribution in the application and discovers the performance bottlenecks by using given bottleneck definitions. The user can query the application execution performance to identify performance problems. The design of the framework is flexible and extensible so it can be tailored based on the actual application execution environment and performance tuning requirement. To demonstrate the usefulness of the framework, we apply the framework on a practical DARPA application and show how it helps to identify performance bottlenecks. The framework helps to automate the performance tuning process and improve the user’s productivity.
I-Hsin Chung, Guojing Cong, David J. Klepacki, Simone Sbaraglia, Seetharami R. Seelam, Hui-Fang Wen
IPDPS4
2006 A Study on the Locality Behavior of Minimum Spanning Tree Algorithms
Guojing Cong, Simone Sbaraglia
HiPC2
2005 Using Dynamic Tracing Sampling to Measure Long Running Programs
abstract
Detailed cache simulation can be useful to both system developers and application writers to understand an application’s performance. However, measuring long running programs can be extremely slow. In this paper we present a technique to use dynamic sampling of trace snippets throughout an application’s execution. We demonstrate that our approach improves accuracy compared to sampling a few timesteps at the beginning of execution by judiciously choosing the frequency, as well as the points in the control flow, at which samples are collected. Our approach is validated using the SIGMA tracing and simulation framework for the IBM Power family of processors.
Jeffrey Odom, Jeffrey K. Hollingsworth, Luiz De Rose, Kattamuri Ekanadham, Simone Sbaraglia
SC5
2004 An Approach for Symbolic Mapping of Memory References
Luiz De Rose, Kattamuri Ekanadham, Simone Sbaraglia
Euro-Par3
2002 SIGMA: a simulator infrastructure to guide memory analysis
abstract
In this paper we present SIGMA (Simulation Infrastructure to Guide Memory Analysis), a new data collection framework and family of cache analysis tools. The SIGMA environment provides detailed cache information by gathering memory reference data using software-based instrumentation. This infrastructure can facilitate quick probing into the factors that influence the performance of an application by highlighting bottleneck scenarios including: excessive cache/TLB misses and inefficient data layouts. The tool can also assist in perturbation analysis to determine performance variations caused by changes to architecture or program. Our validation tests using the SPEC Swim benchmark show that most of the performance metrics obtained with SIGMA are within 1% of the metrics obtained with hardware performance counters, with the advantage that SIGMA provides performance data on a data structure level, as specified by the programmer.
Luiz De Rose, Kattamuri Ekanadham, Jeffrey K. Hollingsworth, Simone Sbaraglia
SC4