The reliability of LDMOSFET as well as FinFET devices has been gaining much interest in the development of various space electronic systems. There are high requirements for nonlinear computation and efficient simulation of radiation-multiphysics effects in these devices, especially in large-scale 3D scenarios, which pose significant challenges. To address these issues, we propose a hybrid numerical method for massively parallel simulation of nonlinear drift-diffusion transport processes in semiconductor devices. The control volume finite element method (CV-FEM) is employed to solve the Poisson, current continuity, and heat conduction equations, which shows strong numerical stability on unstructured meshes compared with the commercial COMSOL Multiphysics software. Further, our self-developed solver is employed to explore the total ionizing dose (TID)-electrothermal synergistic effects in step-doped LDMOSFETs (SD-LDMOSFETs), high-K dielectric SD-LDMOSFETs (HKSD-LDMOSFETs), and multi-fin FinFETs (M-FinFETs). We also implement a combined domain decomposition and J parallel Adaptive Unstructured Mesh applications Infrastructure scheme for parallel computation, where the scalability of our parallel algorithm is examined. It it believed that this study can offer some new insights into the behavior of these devices under radiation and electrothermal coupling, advancing efficient numerical methods to simulate diverse radiation-electrothermal synergistic effects.

Impedance matching circuits (IMCs) are crucial modules in radio frequency (RF) front-end components, devices, and systems, affecting the performance of the whole systems. However, the design process of IMCs has to require intense manual interventions with high computational costs. To alleviate this problem, a novel scheme for inversely designing IMCs is presented in this work based on neural network technology. Such IMC inverse design framework consists of two mapping-based deep neural networks (DNNs). The first one is an untrained generative adversarial network (GAN) that maps from the design requirements to the regularized S-parameters curves. The second one is an inversion network that maps from the S-parameters and the target impedance to the designed circuit parameters. With the cascaded GAN and inversion network, an efficient method for designing IMC-based filtering antenna is introduced, which takes about 1/17 the time compared to the traditional EM-based design and optimization methods. Further, three power amplifiers (PAs) with multiple IMCs are inversely-designed based on the proposed framework. In experimental demonstration, the elaborate prototypes are fabricated and measured, where the measured results fully satisfy the demand performance.

This article presents an 18~30 GHz vector-sum phase shifter for wireless application in the millimeter-wave regime. It is composed of an I/Q signal generator, two variable-gain amplifiers (VGA), and a digital-to-analog converter with a quadrant selector. To attain wideband quadrature signal, a two-stage hybrid based on transformers is proposed to realize the I/Q signal generator. The first- and second-stage hybrids are designed with different resonating frequencies. As a result, the amplitude and phase errors of the I/Q signal generator are significantly decreased in a wide frequency band. In addition, theoretical analysis based on a simplified equivalent-circuit model is performed to guide the circuit implementation, and its correctness is demonstrated by electromagnetic simulation. To mitigate the impact of the VGAs’ parasitics on the phase performance, a capacitive-neutralization technique is applied to cancel parasitics of transistors in the VGAs. A prototype circuit is designed using a 130-nm SiGe BiCMOS process. The measured results show that the circuit achieves a root-mean-square (RMS) amplitude error of less than 1.4 dB and an RMS phase error of 1.4°~3.4° across 18~32 GHz. The tested peak gains of all the phase states are −1~4.5 dB with an input balun ($\approx 1.9$dB loss) and an output balun ($\approx 2$dB loss) at 22 GHz. Also, the input 1-dB compression point and noise figure are tested, which are$\geq $-1 dBm and$\leq 15.5$dB in the targeting frequency band.

In this article, a CMOSKu-band phased-array transmitter with eight elements is demonstrated. To mitigate the measurement time and complexity, a built-in self-test (BIST) circuit is developed in this chip. A fully symmetrical sampling structure is proposed to improve the testing accuracy of the BIST system. To decrease the phase and amplitude errors, two compensation methods based on inductors and capacitors are, respectively, used in the phase shifters and attenuators to minimize severe parasitic effects of transistors in high-frequency bands. In addition, a scalable power divider is developed to save chip area and reduce insertion loss. According to the measurement results, the 5-bit passive phase shifter in each transmitting channel achieves less than 3.6° root-mean-square phase error (RMSPE) and 0.8-dB root-mean-square amplitude error (RMSAE). The transmitter’s attenuators are formed by four bridge-$T/\pi $-type units and achieve less than 0.94-dB RMSAE and RMSPE of 3.2°. Each channel of the transmitter is capable of delivering about 13-dBm linear power at 16 GHz. The BIST system is also employed to detect the phase and amplitude performances of the eight-element transmitter, and the BIST testing errors are less than 10.3% compared to the microwave equipment measurement.

For original paper, see Raychowdhury and Roy, IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol.25, no.1, p.58-65, 2006 January