Even with a very accurate dynamic branch predictor, a superscalar processor must predict instruction fetch addresses no later than the first pipeline stage to avoid suffering pipeline bubbles every time a branch is taken. Unfortunately, branch addresses generally are not known prior to instruction decode. Therefore, some indirect technique is required to identify a branch instruction and enable branch prediction while the branch instruction is being fetched. This is the branch identification problem. Intel Pentium adopts a scheme that solves this problem; however, its scheme assumes an issue rate of two instructions per cycle. An aggressive superscalar processor, issuing more than two instructions per cycle, cannot effectively use that scheme. The authors propose and compare two viable schemes for solving the branch identification problem for wide-issue superscalar processors.>

Simulations indicate a simple modification of existing virtual memory hardware can significantly reduce the number of pins required to transmit address information from processor to off-chip memory. This modification consists of partitioning a TLB so that virtual page numbers are stored in a cache on the processor and corresponding real page numbers are sotred in registers at the memory, making it possible to transmit a small register index instead of the entire real page number.