one pass per subpixel sample) through the hardware rendering pipeline.The resulting image is very high quality, but the performance degrades in proportion to the number of subpixel samples used by the filter function.This paper describes algorithms for accelerating antialiasing in 3D graphics through low-cost custom hardware.The rendering architecture employs a multiple-pass algorithm to perform front-to-back hidden surface removal and shading.Coverage mask evaluation is used to composite objects in 3D.The key advantage of this approach is that antialiasing requires no additional memory and decreases rendering performance by only 30-40% for typical images.The system is image partition based and is scalable to satisfy a wide range of performance and cost constraints.

This paper describes algorithms for implementing accurate rendering of CSG and transparency in a hardware 3D accelerator. The algorithms are based on a hardware architecture which performs front-to-back Z-sorted shading; a multiple-pass algorithm which allows an unlimited number of Z-sorted object layers is also described. The multiple-pass algorithm has been combined with an image partitioning algorithm to improve efficiency, and to improve performance of the resulting hardware implementation.

article Free Access Share on A scalable hardware render accelerator using a modified scanline algorithm Authors: Michael Kelley Apple Computer, Inc., 20525 Mariani Avenue, Cupertino, CA 95014 Apple Computer, Inc., 20525 Mariani Avenue, Cupertino, CA 95014View Profile , Stephanie Winner Apple Computer, Inc., 20525 Mariani Avenue, Cupertino, CA 95014 Apple Computer, Inc., 20525 Mariani Avenue, Cupertino, CA 95014View Profile , Kirk Gould Apple Computer, Inc., 20525 Mariani Avenue, Cupertino, CA 95014 Apple Computer, Inc., 20525 Mariani Avenue, Cupertino, CA 95014View Profile Authors Info & Claims ACM SIGGRAPH Computer GraphicsVolume 26Issue 2July 1992 pp 241–248https://doi.org/10.1145/142920.134069Online:01 July 1992Publication History 22citation718DownloadsMetricsTotal Citations22Total Downloads718Last 12 Months16Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

Current affordable architectures for high-speed display of shaded 3D objects operate orders of magnitude too slowly. Recent advances in floating point chip technology have outpaced polygon fill time, making the memory access bottleneck between the drawing processor and the frame buffer the most significant factor to be accelerated. Massively parallel VLSI system have the potential to bypass this bottleneck, but to date only at very high cost. We describe a new more affordable VLSI solution. A pipeline of triangle processors rasterizes the geometry, then a further pipeline of shading processors applies Phong shading with multiple light sources. The triangle processor pipeline performs 100 billion additions per second, and the shading pipeline performs two billion multiplies per second. This allows 3D graphics systems to be built capable of displaying more than one million triangles per second. We show the results of an anti-aliasing technique, and discuss extensions to texture mapping, shadows, and environment maps.