The emerging edge computing technique provides support for the computation tasks that are delay-sensitive and compute-intensive, such as deep neural network inference, by offloading them from a user-end device to an edge server for fast execution. The increasing offloaded tasks on an edge server are gradually facing the contention of both the network and computation resources. The existing offloading approaches often partition the deep neural network at a place where the amount of data transmission is small to save network resource, but rarely consider the problem caused by computation resource shortage on the edge server. In this paper, we design LoADPart, a deep neural network offloading system. LoADPart can dynamically and jointly analyze both the available network bandwidth and the computation load of the edge server, and make proper decisions of deep neural network partition with a light-weighted algorithm, to minimize the end-to-end inference latency. We implement LoADPart for MindSpore, a deep learning framework supporting edge AI, and compare it with state-of-the-art solutions in the experiments on 6 deep neural networks. The results show that under the variation of server computation load, LoADPart can reduce the end-to-end latency by 14.2% on average and up to 32.3% in some specific cases.

Accurately estimating the rare failure rates for nanoscale circuit blocks (e.g., static random-access memory, D flip-flop, etc.) is a challenging task, especially when the variation space is high-dimensional. In this paper, we propose a novel scaled-sigma sampling (SSS) method to address this technical challenge. The key idea of SSS is to generate random samples from a distorted distribution for which the standard deviation (i.e., sigma) is scaled up. Next, the failure rate is accurately estimated from these scaled random samples by using an analytical model derived from the theorem of “soft maximum.” Our proposed SSS method can simultaneously estimate the rare failure rates for multiple performances and/or specifications with only a single set of transistor-level simulations. To quantitatively assess the accuracy of SSS, we estimate the confidence interval of SSS based on bootstrap. Several circuit examples designed in nanoscale technologies demonstrate that the proposed SSS method achieves significantly better accuracy than the traditional importance sampling technique when the dimensionality of the variation space is more than a few hundred.

Accurately estimating the rare failure rates for nanoscale circuit blocks (e.g., SRAM, DFF, etc.) is a challenging task, especially when the variation space is high-dimensional. In this paper, we propose a novel scaled-sigma sampling (SSS) method to address this technical challenge. The key idea of SSS is to generate random samples from a distorted distribution for which the standard deviation (i.e., sigma) is scaled up. Next, the failure rate is accurately estimated from these scaled random samples by using an analytical model derived from the theorem of “soft maximum”. Several circuit examples designed in nanoscale technologies demonstrate that the proposed SSS method achieves superior accuracy over the traditional importance sampling technique when the dimensionality of the variation space is more than a few hundred.

The continuous technology scaling brings about high-dimensional performance variations that cannot be easily captured by the traditional response surface modeling. In this paper we propose a new statistical regression (STAR) technique that applies a novel strategy to address this high dimensionality issue. Unlike most traditional response surface modeling techniques that solve model coefficients from over-determined linear equations, STAR determines all unknown coefficients by moment matching. As such, a large number of (e.g., 103~105) model coefficients can be extracted from a small number of (e.g., 102~103) sampling points without over-fitting. In addition, a novel recursive estimator is proposed to accurately and efficiently predict the moment values. The proposed recursive estimator is facilitated by exploiting the interaction between different moment estimators and formulating the moment estimation problem into a special form that can be iteratively solved. Several circuit examples designed in commercial CMOS processes demonstrate that STAR achieves more than 20x runtime speedup compared with the traditional response surface modeling.

In this paper, we describe the design and implementation of a distributed operating system for ad hoc networks. Our system simplifies the programming of ad hoc networks and extends total system lifetime by making the entire network appear as a single virtual machine. It automatically and transparently partitions applications into components and dynamically finds them a placement on nodes within the network to reduce energy consumption and to increase system longevity. This paper describes our programming model, outlines the design and implementation of our system and examines the energy efficiency of our approach through extensive simulations as well as validation of a deployment on a physical testbed. We evaluate practical, power-aware, general-purpose algorithms for component placement and migration, and demonstrate that they can significantly increase system longevity by effectively distributing energy consumption and avoiding hotspots.

The introduction of simulation-based analog synthesis tools creates a new challenge for analog modeling. These tools routinely visit 103 to 105 fully simulated circuit solution candidates. What might we do with all this circuit data? We show how to adapt recent ideas from large-scale data mining to build models that capture significant regions of this visited performance space, parameterized by variables manipulated by synthesis, trained by the data points visited during synthesis. Experimental results show that we can automatically build useful nonlinear regression models for large analog design spaces.