Validating the robustness of power distribution in modern IC design is a crucial but very difficult problem, due to the vast number of possible working modes and the high operating frequencies which necessitate the modeling of power grid as a general RLC network. In this paper we provide a characterization of the worst-case current waveform excitations that produce the maximum voltage drop among all possible working modes of the IC. In addition, we give a practical methodology to estimate these worst-case excitations on the basis of a sample of the excitation space acquired via plain circuit simulation. In the course of characterizing the worst-case excitations we also establish that the voltage drop function for RLC grid models has nonnegative coefficients, which has been an open problem so far.

This paper presents a diagnostic test pattern generation (DTPG) framework based upon a Boolean Satisfiability engine. We first propose an enhanced miter-based model for distinguishing fault candidates that can achieve greater efficiency as well as can prove a group of undifferentiable faults. The model can also be used to generate diagnostic tests for distinguishing faults of different fault types. Based on this model, we propose a diagnostic pattern compaction strategy. By exploring "don't cares " at the primary inputs, the number of required diagnostic patterns can be reduced. Experimental results show that the proposed method achieves a greater diagnosis resolution when combined with existing approaches. Also, fewer diagnostic test patterns are needed.

Commonly used pattern sources in simulation-based verification include random, guided random, or design verification patterns. Although these patterns may help bring the design to those hard-to-reach states for activating the errors and for propagating them to observation points, they tend to be very long, which complicates the subsequent diagnosis process. As a key step in reducing the overall diagnosis complexity, we propose a method of generating a shorter error-sequence based on a given long error-sequence. We formulate the problem as a satisfiability problem and employ a SAT solver as the underlying engine for this task. By heuristically selecting an intermediate state S/sub i/ which is reachable by the given long sequence, the task of finding the transfer sequence from the initial state to the target state can be divided into two easier tasks - finding a transfer sequence from the initial state to S/sub i/ and one from S/sub i/ to the target state. Our preliminary experimental results on public benchmark circuits show that the proposed method can achieve significant reduction in the length of the error sequences.

The developments of efficient SAT solvers have attracted tremendous research interest in recent years. The merits of these solvers are often compared in terms of their performance based upon a wide spread of benchmarks. In this paper, we extend an earlier-proposed solver design concept called (SCGL) Signal Correlation Guided Learning that is ATPG-based into a family of heuristics. Along with this SCGL family of heuristics, we classify benchmark examples according to their performance using the SCGL heuristics. With this study, we identify the class of problems that are uniquely suitable to be solved by using the SCGL approach. In particular, for solving difficult circuit-based problems at INTEL, our SCGL-based ATPG solver is able to achieve at least an order of magnitude speedup over the state-of-the-art SAT solvers. Our conclusion is that SCGL is an unique solver design concept that can complement heuristics proposed by others for solving circuit-oriented difficult problems.

This paper addresses the problem of verifying the correctness of gate-level implementations of large synchronous sequential circuits with respect to their higher level specifications in a hardware description language (HDL). The verification strategy is to verify containment of the finite state machine (FSM) represented by the HDL description in the gate-level FSM by computing pairs of compatible states. This formulation of the verification problem dissociates the verification process from the specification of initial states, whose encoding may be unknown or obscured during optimization and also enables verification of reset circuitry. To make verification of large circuits with merged data path and control tractable, the concept of strong containment is introduced. This is a conservative approach which exploits correspondence between data path-registers in the two descriptions without requiring any correspondence between the control units. We also present an important result and associated proof that computation of pairs of equivalent or compatible states can be achieved by considering subsets of the circuit outputs. Consequently, verification of circuits with large and diverse input-output sets, which was previously intractable due to lack of a single effective variable order for the binary decision diagrams (BDD's), is now feasible. Experimental results are presented for the verification of several industry level circuits.

Automatic verification of implementations against their specifications in the design hierarchy is largely based on state machine comparison. This paper presents a simple technique that exploits information about correspondence between registers in the data path to enable abstraction of data path registers and make automatic verification of circuits with large date paths tractable. Correspondence between registers which encode the control states is not required. This generality enables efficient verification of large circuits with data paths structured differently, as well as verification against specifications devoid of structural information. Results are presented for the verification of realistic circuits at different levels in the design hierarchy.>