Single-electron transistors (SETs) exhibit a unique characteristic of Coulomb oscillation which can find many digital applications with area efficiency. More specifically, both MOS and SET devices can be used to implement XOR gates with almost the same area costs regardless of the number of their inputs, outperforming pure CMOS solutions. As multiple-input XOR gates are abundant in the finite field polynomial multiplication which represents the most frequent computation in elliptic curve cryptosystem, hybrid SET-MOS technology can substantially reduce the area cost for this application. This paper presents polynomial multiplication architectures with hybrid SET-MOS transistors and explores Karatsuba-algorithm based multiplication for further area optimization. Simulations show that the proposed hybrid SET-MOS implementations can typically provide around 37% savings in terms of gate count compared to their traditional CMOS counterparts.

Reliability analysis for combinational logic circuits can be computationally complex due to a large number of inputs and possible signal correlations. This paper presents a triple-point model for circuit-level reliability analysis by using a closed-form expression in terms of output signal probabilities from both erroneous and error-free circuits. Since signal probabilities are relatively easier to be obtained by analysis and/or simulation, this work can simplify and speed up the analysis process for large-scale circuits. Simulation results with benchmark circuits show that the proposed model produces an average error of 2% in estimating circuit reliability, compared to 12% with the existing related work.

With CMOS technology approaching the nanometer scale, probabilistic design has received much attention from the research community. In this paper, we propose a power optimization methodology for probabilistic logic circuits with stochastic components. Inexactness in circuits allows the local reliability-power tradeoff of unreliable components, and provides us with design space for power optimization. The proposed approach aims to minimize the power cost of circuits under certain error rate constraints. We show that the proposed method outperforms other intuitive approaches by a factor of 2.5X, on average, in terms of power costs under a same target error rate.

This paper presents a single-electron tunneling (SET) based implementation of the conscience mechanism in order to improve the Kohonen learning by accelerating its convergence rate. This conscience mechanism biases the competition process so that all the processing elements can be brought into desired solutions quickly. By utilizing the electron transfer characteristics of novel single electron devices (SEDs), the proposed circuit architecture can realize the conscience mechanism in a more compact way. System-level simulations are presented to verify the effectiveness of the proposed implementation. Transistor-level simulations (including Monte Carlo simulations) are also performed with analytical models where the behavior of devices is described in Verilog modeling language. Extensive simulation results show the advantages of proposed architecture in terms of area and power cost.

In this paper, we investigate the design of binary tree multipliers based on multi-input counters using hybrid MOS and single-electron transistors (SETs). Our focus is on the design of phase-modulated counters which can be implemented with only a few MOSFETs and multi-gate SETs. In order to address some practical issues associated with SET/MOS hybrid circuits, we present an enhanced version of the counters to deal with temperature effect, reliability improvement, and operating speed with multipliers. Simulation results with the proposed phase-modulated (7:3) counter show that it is able to work at room temperature with a delay of 1.5 ns, power dissipation of 4.1 μW at frequency of 100 MHz, and maximum tolerable background charges of up to 0.2e with the worst-case delay of 3 ns.

This paper proposes a frequency synthesizer using single-electron transistor (SET)/MOS hybrid architectures for binary multiplier design. The main idea is to first convert the operands from their digital representation to frequency representation, and then perform multiplication in the frequency domain before converting the result back to the digital representation. The major merits of the proposed method include: 1) simplified implementation of binary multiplication and 2) high immunity against the background charges inherent in SET islands. Both circuit design and simulation are provided to show the effectiveness of the approach.

As a major contributor to the Bose-Chaudhuri-Hocquenghem (BCH) decoder's power consumption, Chien search is a critical step in the binary BCH decoding process for many portable applications. This paper proposes a new low-power design strategy by applying register transfer level (RTL) power management with significant power savings. The proposed Chien search is implemented for a (255, 187, 9) code in CMOS 0.18-μm technology, and simulations show 34% power improvement over the conventional method.

Chien search is a computation-intensive VLSI design in BCH (Bose-Chaudhuri-Hocquenghem) decoders for a variety of applications such as digital video and data storage. Existing low power approaches to this subject are effective only for single-bit error case, and their power efficiency decreases dramatically for multiple-bit-correcting code. This paper presents a novel approach of using register-transfer-level (RTL) power management in the search process, leading to significant power savings for BCH codes with higher correction capability. A (255, 187, 9) BCH code is implemented in 0.18μm CMOS technology as an example.

This paper provides an analytical approach to evaluate the performance of anti-collision protocols in radio-frequency identification (RFID) systems. The analysis is given at protocol-level using such performance metrics as the number of state transitions and clock cycles involved in the protocols’ state diagrams, their power and energy dissipation. Discussion and comparison are based on worst-case scenario that represents the process of identifying the last tag when multiple tags are simultaneously available in the system. A new protocol is also proposed for performance improvement.

In this paper we investigate two different multi-island structures (namely mesh-structure and clique-structure) based on Single-Electron Tunneling (SET) technology, and study the experimental behaviors in terms of their tolerance to random background charges (RBCs) which are a big concern with SET logic. As an alternative redundancy scheme, both structures are applied to an SET-based NAND logic gate for detailed discussions. Our main objective is to show that the proposed multi-island structures are more tolerant to RBCs over the islands when compared with single-island SET logic. Further comparison between the two structures is also shown through the experiments.

This paper presents new quasi-static single-phase energy recovery logic (QSSERL) which, unlike any other existing adiabatic logic family, uses single sinusoidal supply-clock without additional voltages. This not only ensures lower energy dissipation, but also simplifies the clock design which would be otherwise more complicated due to the signal synchronization requirement. It is demonstrated that QSSERL circuits operate as fast as conventional two-phase energy recovery logic counterparts. HSPICE simulation with an 8-bit logarithmic lookahead adder (LLA) using static CMOS, CAL (an existing single-phase based energy recovery logic), and QSSERL shows that the QSSERL adder consumes only 56% of energy as with its static CMOS counterpart at 10MHz and achieves better energy efficiency than CAL.

In this paper we propose an approach of providing the best power-delay tradeoff for combinational circuits. This is done by so-called power-oriented delay budgeting which is to combine the delay-budgeting technique with aggressive power optimization. We discuss the impacts that both discrete cell library and circuit topology may have on the potential power reduction. Experimental results show that up to 65% (an average of 35%) power savings can be achieved without any delay penalty.

For low-cost RFID systems, the design of passive tags is a key issue in anti-collision protocols where lower power consumption allows a longer working distance between tags and the reader. In this paper, we look at anti-collision protocols in tags ’ processing for their power optimization. We propose a new criterion, which takes into account both energy consumption and time complexity, to evaluate anti-collision protocols. An improved protocol is also presented for power savings.

In the past few years, gate duplication has been studied as a strategy for cutset minimization in partitioning problems. This paper addresses the problem of delay optimization by gate duplication. We present an algorithm to solve the gate duplication problem. It traverses the network from primary outputs(PO) to primary inputs(PI) in topologically sorted order evaluating tuples at the input pins of gates. The tuple's first component corresponds to the input pin required time if that gate is not duplicated. The second component corresponds to the input pin required time if that gate were duplicated. After tuple evaluation the algorithm traverses the network from PI to PO in topologically sorted order, deciding the gates to be duplicated. The last and final traversal is again from PO to PI, in which the gates are physically duplicated. Our algorithm uses the dynamic programming structure. We report delay improvements over other optimization methodologies. Gate duplication, along with other optimization strategies, can be used for meeting the stringent delay constraints in today's ultra complex designs.

Optimizing power consumption at high-level is a critical step towards power-efficient digital system designs. This paper addresses the power management problem by scheduling a given control-dominated data flow graph. We discuss delay and power issues with scheduling, and propose an improvement algorithm for insertion of so-called soft edges which enable power optimization under timing constraints. Power savings obtained by our approach on tested circuits range between 15 % and 30 % of the initial power dissipation.

This paper presents an activity-sensitive clock tree construction technique for low power design of VLSI clock networks. We introduce the term of node difference based on module activity information, and show its relationship with the power consumption. A binary clock tree is built using the node difference between different modules to optimize the power consumption due to the interconnections (i.e., clock gating signals and clock edges). We also develop a method to determine gating signals with minimum number of transitions. After the clock tree is constructed, the gating signals are optimized for further power savings.

Supply voltage is one of the dominant factors that determine the timing performance and power consumption of VLSI chips. For digital systems with a single supply voltage, some logic devices typically operate faster or more frequently than necessary, consuming extra power. This motivates the need for multiple-voltage design for an aggressive power optimization as slow operation allows a reduced voltage level. While the past few years have seen some successful examples from behavioral- and logic-level synthesis, physical designers are facing the challenges under such a new design environment. This talk discusses the physical aspects of multiple-voltage design, including the latest approaches to emerging problems such as voltage interface, clock distribution, power/ground network, and place-and-route (for more info, visit the web site at: http://www.vlsi.uwindsor.ca/~cchen). The goal is to enable designers to deal with key issues in implementation of multiple-voltage chips.

Presents a new concept of potential slack to measure so-called potential performance of digital circuits. Potential means how much improvement could be made in the future in terms of timing, area, and power dissipation. Predicting potential performance helps the circuit designers make good design decisions at a specific level of abstraction. The authors describe two algorithms for potential slack: an optimal algorithm and a fast greedy algorithm. The former is based on a maximal-independent set on transitive graphs, while the latter focuses on potential slack estimation in a greedy manner. Applications to gate- and physical-level design problems are provided to show the effectiveness of potential slack in predicting the potential performance of digital circuits.

The rectilinear Steiner tree (RST) problem is of essential importance to the automatic interconnect optimization for VLSI design. In this paper, we present a class of probability-based approaches toward the best solutions under statistical sense and show their performance in comparison with the state-of-the-art algorithm. Experiments conducted on both small- and large-size problems indicate that the proposed approaches lead to promising results in terms of wire length and/or CPU time. The potential advantages with our technique are also discussed for further applications.

We propose a timing driven gate duplication algorithm for the technology independent phase. Our algorithm is a generalization of the gate duplication strategy suggested in [1]. Our technique gets a more global view by duplicating multiple gates at a time. We compare the minimum circuit delay obtained by SIS [2] with the delay obtained by using our gate duplication. Results show that up to 11% improvement in delay can be obtained. Our algorithm does not have an adverse effect on the overall synthesis time, indicating that gate duplication is an efficient strategy for timing optimization.

In this paper, we investigate reducing the power consumption of a synchronous digital system by minimizing the total power consumed by the clock signals. We construct activity-driven clock trees wherein sections of the clock tree are turned off by gating the clock signals. Since gating the clock signal implies that additional control signals and gates are needed, there exists a tradeoff between the amount of clock tree gating and the total power consumption of the clock tree. We exploit similarities in the switching activity of the clocked modules to reduce the number of clock gates. Assuming a given switching activity of the modules, we propose three novel activity-driven problems: a clock tree construction problem, a clock gate insertion problem, and a zero-skew clock gate insertion problem. The objective of these problems is to minimize the system's power consumption by constructing an activity-driven clock tree. We propose an approximation algorithm based on recursive matching to solve the clock tree construction problem. We also propose an exact algorithm employing the dynamic programming paradigm to solve the gate insertion problems. Finally, we present experimental results that verify the effectiveness of our approach. This paper is a step in understanding how high-level decisions (e.g., behavioral design) can affect a low-level design (e.g., clock design).

In this paper, we present an approach for applying two supply voltages to optimize power in CMOS digital circuits under the timing constraints. Given a technology-mapped network, we first analyze the power/delay model and the timing slack distribution in the network. Then a new strategy is developed for timing-constrained optimization issues by making full use of stacks. Based on this strategy, the power reduction is translated into the polynomial-time-solvable maximal-weighted-independent-set problem on transitive graphs. Since different supply voltages used in the circuit lead to totally different power consumption, we propose a fast heuristic approach to predict the optimum dual-supply voltages by looking at the lower bound of power consumption in the given circuit. To deal with the possible power penalty due to the level converters at the interface of different supply voltages, we use a "constrained F-M" algorithm to minimize the number of level converters. We have implemented our approach under an SIS environment. Experiment shows that the resulting lower bound of power is tight for most circuits and that the predicted "optimum" supply voltages are exactly or very close to the best choice of actual ones. The total power saving of up to 26% (average of about 20%) is achieved without degrading the circuit performance, compared to the average power improvement of about 7% by the gate sizing technique based on a standard cell library. Our technique provides the power-delay tradeoff by specifying different timing constraints in circuits for power optimization.

Abstract ⎯ This paper proposes to use voltage-scaling (VS) and gate-sizing (GS) simultaneously for reducing power consumption without violating the timing constraints. We present algorithms for simultaneous VS and GS based on the Maximum-Weighted-Independent-Set problem. We describe the slack distribution of circuit, completeness of gate library and discreteness of supply voltage, and discuss their effects on power optimization. Experimental results show that the average power reduction ranges from 23.3 % to 56.9 % over all tested circuits. I.

This paper proposes the concept of potential slack and shows that it is an effective metric of combinational circuit performance. We provide several methods for estimating potential slack and prove one (a maximal-independent-set based algorithm) in particular which works best. Experiments in gate sizing show that potential slack provides 100% correct prediction for circuit area optimization. We also explore the role of potential slack in timing-driven placement.

The dual-voltage approach has emerged as an effective and practical technique for power reduction. In this paper, we explore power optimization with dual supply voltages under given timing constraints. By analyzing the relations among the timing slack, delay and power consumption in a given circuit, we relate the voltage-scaling power optimization to the maximal weighted independent set (MWIS) problem, which is polynomial-time solvable on a transitive graph. Then we develop a provably good lower-bound algorithm based on MWIS to generate the lower bound of the power consumption. Also, we propose a fast approach to predict the optimum supply voltages. The maximum power reduction is obtained by using a modified lower-bound algorithm with optimum voltages. Experimental results show that the resulting lower bound is tight for most circuits and that the estimated optimum supply voltage is exactly, or very close to, the best choice of actual voltages.

We present an approach for applying two supply voltages to optimize power in CMOS digital circuits under the timing constraints. Given a technology-mapped network, we first analyze the timing slack distribution and power/delay model within the circuit. The power reduction is then translated into the Maximal-Weighted-Independent-Set (MWIS) problem. We develop an effective power optimization algorithm based on MWIS. To reduce the possible power penalty of level converters (LCs) at the interface of two supply voltages, we use a "constrained" F-M algorithm to minimize the number of LCs. Experimental results show that the total power saving up to 35% (average of about 19%) is achieved without degrading the circuit performance. The power-delay tradeoff is provided by specifying different timing constraints for power optimization.