We present an efficient technique to reduce the switching activity in a technology-mapped CMOS combinational circuit based on local logic transformations. The transformations consist of adding redundant connections or gates so as to reduce switching activity. We describe simple and efficient procedures, based on logic implication, for identifying the sources and targets of the redundant connections. Additionally, we give procedures that permit the designer to trade-off power and delay after the transformations. Results of experiments on both the MCNC benchmark circuits and the circuits of a PowerPC microprocessor chip are given. The results indicate that significant power reduction of a CMOS combinational circuit can be achieved with very low area overhead, delay penalty, and computational cost.

We address the problem of state encoding for synchronous finite state machines (FSM's), targeted for low power design. Most previous work in FSM state encoding has been focused on minimizing chip area and does not consider switching activity of the circuit. As a result, this does not always lead to a power efficient implementation. Especially in CMOS circuits, the switching activity is a very important factor in power dissipation. In this work, we define a function /spl lambda/ for automatic tradeoff between switching activity and area that contribute to power dissipation. /spl lambda/ is used in determining the encoding affinity between states and is observed to be related to the number of states of a FSM in our experiments. A state encoding algorithm, based on hypercube embedding, is proposed to find encodings of states such that the sum of bit toggles between each pair of states times the encoding affinity between them is minimized. Results over a wide range of MCNC benchmark examples which show the efficacy of our technique are presented.

Previous algorithms on rectangular dual graph floorplanning generate general floor-plans which include the class of nonsliceable floorplans. We examine the framework of generating sliceable floorplans using the rectangular dual graph approach and present an algorithm that generates a sliceable floorplan if the input graph satisfies certain sufficient conditions. For general input, the algorithm is still able to generate sliceable floorplans by introducing pseudomodules where the areas occupied by the pseudomodules are used for wiring. For an n-vertex adjacency graph, the algorithm generates a sliceable floorplan in $O( n\log n + hn )$ time where h is the height of the sliceable floorplan tree.

Given a sliceable floorplan and cell sizes, Otten and Stockmeyer (1983) presented an algorithm to find an optimal implementation for each cell. The authors consider a generalized optimal sizing problem on a set of slicing trees related to an adjacency graph. For computation efficiency, they combine the tree enumeration and sizing procedures in a unified algorithm where floorplan trees and sizes are computed simultaneously. The tree enumeration is based on adjacency graph of the input cells, which ensures that the adjacency requirements of the cells are preserved. Time complexity of the algorithm is analyzed and experimental results using MCNC benchmarks are reported.>