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Abhinav Agrawal 0002

dblp:73/3655-2 · DBLP profile ↗
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2ranked-venue papers
1as first author
0since 2021 · last 2006
0000-0001-7053-0144ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%
Theoretical computer science
1 paper
Quantum computing and quantum information · 100%

Topics — the 3 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
logic synthesis
0.112006
An Algorithm for Synthesis of Reversible Logic Circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2006
Electronic design automation › logic synthesis › non-conventional logic synthesis
reversible logic synthesis
0.112006
An Algorithm for Synthesis of Reversible Logic Circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2006
Quantum computing and quantum information
quantum circuit synthesis
0.112006
An Algorithm for Synthesis of Reversible Logic Circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2006

Methods — techniques the papers use, named apart from their topics

toffoli gate library · 0.1priority-based search tree · 0.1positive-polarity reed-muller expansion · 0.1
YearPublicationVenuePosition
2006 An Algorithm for Synthesis of Reversible Logic Circuits
abstract
Reversible logic finds many applications, especially in the area of quantum computing. A completely specified n-input, n-output Boolean function is called reversible if it maps each input assignment to a unique output assignment and vice versa. Logic synthesis for reversible functions differs substantially from traditional logic synthesis and is currently an active area of research. The authors present an algorithm and tool for the synthesis of reversible functions. The algorithm uses the positive-polarity Reed-Muller expansion of a reversible function to synthesize the function as a network of Toffoli gates. At each stage, candidate factors, which represent subexpressions common between the Reed-Muller expansions of multiple outputs, are explored in the order of their attractiveness. The algorithm utilizes a priority-based search tree, and heuristics are used to rapidly prune the search space. The synthesis algorithm currently targets the generalized n-bit Toffoli gate library. However, other algorithms exist that can convert an n-bit Toffoli gate into a cascade of smaller Toffoli gates. Experimental results indicate that the authors' algorithm quickly synthesizes circuits when tested on the set of all reversible functions of three variables. Furthermore, it is able to quickly synthesize all four-variable and most five-variable reversible functions that were in the test suite. The authors also present results for some benchmark functions widely discussed in literature and some new benchmarks that the authors have developed. The algorithm is shown to synthesize many, but not all, randomly generated reversible functions of as many as 16 variables with a maximum gate count of 25
Pallav Gupta, Abhinav Agrawal 0002, Niraj K. Jha
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2
2004 Synthesis of Reversible Logic
abstract
A function is reversible if each input vector produces a unique output vector. Reversible functions find applications in low power design, quantum computing, and nanotechnology. Logic synthesis for reversible circuits differs substantially from traditional logic synthesis. In this paper, we present the first practical synthesis algorithm and tool for reversible functions with a large number of inputs. It uses positive-polarity Reed-Muller decomposition at each stage to synthesize the function as a network of Toffoli gates. The heuristic uses a priority queue based search tree and explores candidate factors at each stage in order of attractiveness. The algorithm produces near-optimal results for the examples discussed in the literature. The key contribution of the work is that the heuristic finds very good solutions for reversible functions with a large number of inputs.
Abhinav Agrawal 0002, Niraj K. Jha
DATE1