We describe a high-level system for granular data-parallel programming called GLU in which parallel applications are described as succinct implicitly parallel intensional compositions using sequential imperative functions. We show how different architecture-independent parallel programs can be generated from the high-level application description. We also show how GLU enables functional debugging of parallel applications without requiring their parallel execution. To illustrate the efficiency of parallel programs generated in GLU, we consider the results of a performance study of three real parallel GLU applications, executed on two different parallel computers. Finally, we compare GLU to other very high-level systems for granular data-parallel programming. © 1997 by John Wiley & Sons, Ltd.

MPEG (Moving Pictures Expert Group) is an industrial standard for video processing and is widely used in multimedia applications in the Internet. However, no security provision is specified in the standard. We conducted an experimental study of previously proposed selective encryption schemes for MPEG video security. This study showed that these methods are inadequate for sensitive applications. We discuss the tradeoffs between levels of security and computational and compression efficiency.

Analog equalizers offer potentially higher speed, lower power and smaller die area than their digital counterparts. Assuming adequate analog forward equalizers are available, we present different integrated circuit (IC) architectures for analog-based decision feedback equalizers, and the strengths and weaknesses of each implementation are discussed.>

The accuracy and speed characteristics of implementations of several line integration models required for Radon (1917) transform (used for computed tomography image reconstruction) and backprojection computations are described and compared. The fixed-point number system used is evaluated by error comparisons to identical floating-point calculations. An expandable multiprocessor architecture for high-speed computation that has been realized as a prototype using commercially available digital signal processor (DSP) chips as the basic processing elements is described. The simulated performances of two popular DSP chips for this application are discussed and compared. Performance characteristics of the complete prototype hardware system are presented. The computational speed of a four-chip system is measured to be more than 190 times better than that of a Sun 3/160 with a math coprocessor. The architecture and prototype organization are not dependent on the DSP chip chosen, and substitution of the most up-to-date DSP chips can yield even better speed performance.>

A unified Radon-transform/back-projection IC that is capable of performing the forward Radon transform and back-projection computations in a multiprocessor array architecture is being designed in a CMOS technology. The architecture of the IC and related design considerations are presented. This chip would make possible high-quality image reconstruction to 12-b resolution at video rates.>

A new architecture for contour tracing of black-and-white images is described. This architecture uses parallelism and pipelining to achieve a significant increase in processing speed over previous tracers. An array of identical processors suitable for VLSI implementation is used. The array approach facilitates expansion to handle arbitrarily large images. The processors trace independently, thereby providing fully parallel, high-speed operation. A postprocessor links the partial contours created by the subdivision of the input image. Simulation results for compression ratio and number of operations are presented.>